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EE323000 積體電路設計導論 Introduction to HSPICE Tutor : Chien-Chen Lin 2015/4/12.

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Presentation on theme: "EE323000 積體電路設計導論 Introduction to HSPICE Tutor : Chien-Chen Lin 2015/4/12."— Presentation transcript:

1 EE 積體電路設計導論 Introduction to HSPICE Tutor : Chien-Chen Lin 2015/4/12

2 LARC_Memory (Prof. M. F. Chang) HSPICE # 2 EE Dept., NTHU, Taiwan What is SPICE  Simulation Program with Integrated Circuit Emphasis  PSPICE 、 SPECTRE use graphical interface like  HSPICE use text interface like Mn vd vg vss vss n_18 w=1u l=0.18u m=1 device name net1 net2……. type parameter value SBT-SpiceStar-HSpice H-SpiceP-Spice SPECTRE SPICE2 SPICE2G.6 SPICE3 etc SPICE

3 LARC_Memory (Prof. M. F. Chang) HSPICE # 3 EE Dept., NTHU, Taiwan Prepare files Hspice Library cic018.l Netlist inv.spi Simulation file Hw1.sp

4 LARC_Memory (Prof. M. F. Chang) HSPICE # 4 EE Dept., NTHU, Taiwan Example(inverter analysis) * title.prot.lib “cic018.l” TT.unprot.inc “inv.spi”.option post x1 VIN VOUT VDD GND inv C1 out p v1 VDD v2 GND 0 0 v3 VIN 0 0.dc v probe V(VOUT).end Set up Circuit description Power supply Analysis File end VDD VSS A Z X1 3.3V

5 LARC_Memory (Prof. M. F. Chang) HSPICE # 5 EE Dept., NTHU, Taiwan Basic syntax  第一行 HSPICE 不會讀到,一般用來註明 TITLE 。  用 ﹡來當作整行註解;用$來當作該行部分註解。  SPICE code 不分大小寫,且擺放位置先後順序可對調。  Net 用 0 、 gnd 來命名皆表示該 net 接地。  結尾要打.END 。

6 LARC_Memory (Prof. M. F. Chang) HSPICE # 6 EE Dept., NTHU, Taiwan Device table  Device table Unit table

7 LARC_Memory (Prof. M. F. Chang) HSPICE # 7 EE Dept., NTHU, Taiwan Device  Resistor Rxxx net1 net2 R=? Ω Ex : R1 v1 v2 100  Inductor Lxxx net1 net2 L=? H Ex : L2 v3 v4 1n  Capacitor Cxxx net1 net2 C=? F Ex : C3 v5 v6 2p

8 LARC_Memory (Prof. M. F. Chang) HSPICE # 8 EE Dept., NTHU, Taiwan Device  Mxxx drain gate source body channel-type width length m . NMOS body is the most negative bias (GND) . PMOS body is the most positive bias (VDD)  Ex : Inverter MP Z A VDD VDD p_18 w=1u l=0.18u m=2 MN Z A GND GND n_18 w=1u l=0.18u m=1

9 LARC_Memory (Prof. M. F. Chang) HSPICE # 9 EE Dept., NTHU, Taiwan Corner  FF: Fast NMOS and Fast PMOS  TT: Typical NMOS and PMOS  SS: Slow NMOS and Slow PMOS  SF: Slow NMOS and PMOS  FS: Fast NMOS and Slow PMOS

10 LARC_Memory (Prof. M. F. Chang) HSPICE # 10 EE Dept., NTHU, Taiwan Sub-circuit .subckt sub-circuit name port name Your sub-circuit schematic.ends  Ex : Inverter (inv.spi) *title.subckt inv A Z VDD GND MP Z A VDD VDD pch w=1u l=0.35u m=2 MN Z A GND GND nch w=1u l=0.35u m=1.ends

11 LARC_Memory (Prof. M. F. Chang) HSPICE # 11 EE Dept., NTHU, Taiwan Example(inverter DC analysis) * title.prot.lib “cic018.l” TT.unprot.inc “inv.spi”.option post x1 VIN VOUT VDD GND inv C1 out p v1 VDD v2 GND 0 0 v3 VIN 0 0.dc v probe V(VOUT).end Set up Circuit description Power supply Analysis File end VDD VSS A Z X1 1.8V

12 LARC_Memory (Prof. M. F. Chang) HSPICE # 12 EE Dept., NTHU, Taiwan Example(inverter DC analysis) * title.prot.lib “cic018.l” TT.unprot.inc “inv.spi”.option post.param vin = 0 x1 VIN VOUT VDD GND inv C1 out p v1 VDD v2 GND 0 0 v3 VIN 0 ‘vin’.dc vin probe V(VOUT).end Set up Circuit description Power supply Analysis File end VDD VSS A Z X1 1.8V

13 LARC_Memory (Prof. M. F. Chang) HSPICE # 13 EE Dept., NTHU, Taiwan Source  Voltage source Vxxx net1 net2 DC=? V AC=? V Ex : Vsupp vdd vss DC=3.3 Ex : Vin vi vss DC=2 AC=1 Vxxx net1 net2 SIN vdc vamp freq td df phase Ex : VSIN in 0 SIN Meg Vxxx net1 net2 PULSE v1 v2 td tr tf pw period Ex : VPULSE in 0 PULSE n 0.1n 0.1n 0.9n 2n Vxxx net1 net2 PWL t1 v1 t2 v2 t3 v3…….. Ex : VPWL in 0 PWL 0 0 1n 0 1.1n 3.3 2n n 0 3n 0  Current source Ixxx net1 net2 DC=? A AC=? AEx : Isupp vdd vss DC=3.3

14 LARC_Memory (Prof. M. F. Chang) HSPICE # 14 EE Dept., NTHU, Taiwan PULSE & PWL td tftr pw period v1 v2 V0 vp 0 ( n 0.1n 0.1n 0.9n 2n) V0 vpwl 0 PWL( 0n 1.8 1n 0 2n 0 2.1n 1.8)

15 LARC_Memory (Prof. M. F. Chang) HSPICE # 15 EE Dept., NTHU, Taiwan Analysis .OP: Analyze operation point of nodes in circuit. -> *.lis Syntax..OP Example..OP .DC: DC analysis to sweep parameter, source and temperature values. - > *.sw* Syntax..DC Example..DC Vgs .AC: AC analysis to sweep frequency. -> *.ac* Syntax..AC Example..AC DEC 101KHz10MHz .Tran : Transient analysis to sweep time. -> *.tr* Syntax..Tran Example..Tran 1ns 1us

16 LARC_Memory (Prof. M. F. Chang) HSPICE # 16 EE Dept., NTHU, Taiwan Analysis .Probe : Probe the observation will not show in the result file but can be seen at awaves.probe V(net) I(device) .Print : Print the observation in the result file.print V(net) I(device) .Plot : Plot the observation in the result file (Funny Plot).plot V(net) I(device)

17 LARC_Memory (Prof. M. F. Chang) HSPICE # 17 EE Dept., NTHU, Taiwan Optional Analysis  SWEEP: Additional nested sweep analysis. Sweep parameter, source or temperature values but not model parameters. Syntax. SWEEP or SWEEP Example..DC Vds SWEEP Vgs AC DEC 10 1K 10M SWEEP RL 10K 30K 10K.Tran 1ns 1us SWEEP TEMP .ALTER: Alter condition and repeat analysis. Syntax..ALTER (usually combines with.param) Example..ALTER.lib ‘cic018.l’ ff.ALTER.lib ‘cic018.l’ ss.END

18 LARC_Memory (Prof. M. F. Chang) HSPICE # 18 EE Dept., NTHU, Taiwan Measure  Function from to Syntax..meas FUNC From To Ex:.meas Tran MaxValue MAX V(out) from=1n to=10n Syntax..meas FUNC AT Ex:.meas DC DC_Gain DERIV V(out) at=‘0.5*3.3’  FUNC can be MIN, MAX, AVG, RMS, DERIV, INTEG  PARAM Syntax..meas PARAM=(‘’) Ex:.meas AC AC_GAIN PARAM=(‘Vdb(out)-Vdb(in)’)

19 LARC_Memory (Prof. M. F. Chang) HSPICE # 19 EE Dept., NTHU, Taiwan Examples  找出 output 在 1n 到 10n 的最高值 l.meas Tran MaxValue MAX V(out) from=1n to=10n  找出 output 在 0.5VDD 的斜率 l.meas DC DC_Gain DERIV V(out) at=‘0.5*3.3’

20 LARC_Memory (Prof. M. F. Chang) HSPICE # 20 EE Dept., NTHU, Taiwan Measure  Trigger and Target Syntax..meas TRIG TARG Ex:.meas tran SettleTime Trig V(out) val=0V rise=1 Targ V(out) + val=1V cross=last  Analysis can be DC, AC, Tran  Val means value of V(net)  Slew can be rise, fall, cross (special word “last”)

21 LARC_Memory (Prof. M. F. Chang) HSPICE # 21 EE Dept., NTHU, Taiwan Example.meas tran SettleTime Trig V(out) val=0V rise=1 Targ V(out) + val=1V cross=last Trig val=0v rise=1 Targ val=1V cross=1 Targ val=1V cross=last

22 LARC_Memory (Prof. M. F. Chang) HSPICE # 22 EE Dept., NTHU, Taiwan Measure  Find When Syntax..meas FIND WHEN + Slew Ex:.meas AC Phase FIND VP(out) WHEN VdB(out)=0 fall=1  Find At Syntax..meas FIND AT Ex:.meas TRAN Volt Find V(out) at=10n

23 LARC_Memory (Prof. M. F. Chang) HSPICE # 23 EE Dept., NTHU, Taiwan How to run HSPICE  Make sure all files are in the same folder you can type ls to check  Enter that folder, type hspice xxx.sp >! xxx.lis or hspice -i xxx.sp -o xxx.lis  If there is no error, terminal will print out job concluded otherwise, terminal will print out job aborted Open xxx.lis file check error. It will tell you everything.

24 LARC_Memory (Prof. M. F. Chang) HSPICE # 24 EE Dept., NTHU, Taiwan SPICE explorer  Type sx & at terminal

25 LARC_Memory (Prof. M. F. Chang) HSPICE # 25 EE Dept., NTHU, Taiwan SPICE explorer

26 LARC_Memory (Prof. M. F. Chang) HSPICE # 26 EE Dept., NTHU, Taiwan SPICE explorer Double click

27 LARC_Memory (Prof. M. F. Chang) HSPICE # 27 EE Dept., NTHU, Taiwan SPICE explorer Double click

28 LARC_Memory (Prof. M. F. Chang) HSPICE # 28 EE Dept., NTHU, Taiwan Basic syntax(inverter DC analysis) * title.prot.lib “mm0355v.l” TT.unprot.inc “inv.spi”.option post x1 IN OUT VDD GND inv C1 out p v1 VDD 0 3 v2 GND 0 0 v3 IN 0 0.dc v probe V(OUT).end include library and set corner condition call inv sub-circuit voltage source file end title include netlist simulation analysis output node voltage waveform post


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