1. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Sorting is
generic (AddressBits : natural;
StateMaxValue : natural;
NumberOfColumns : natural;
RAM_address_size : integer := 8;
RAM_words : integer := 32;
ROM_words : integer := 32;
RAM_data : integer := 8;
Lstack_size : integer := 32 );
Port ( ASCII_in : in STD_LOGIC_VECTOR (7 downto 0);
ASCII_out : out STD_LOGIC_VECTOR (7 downto 0);
Address_in : in STD_LOGIC_VECTOR (AddressBits - 1 downto 0);
Address_out : out STD_LOGIC_VECTOR (AddressBits - 1 downto 0);
clkVGA : in STD_LOGIC;
rst : in STD_LOGIC;
WE_in : in STD_LOGIC;
WE_out : out STD_LOGIC;
Button : in std_logic_vector(3 downto 1);
Led : out std_logic_vector(7 downto 0);
Switch : in std_logic_vector(7 downto 0);
segments : out std_logic_vector(7 downto 0);
displays : out std_logic_vector(3 downto 0));
end Sorting;
architecture Behavioral of Sorting is
signal clk : std_logic;
signal counter : std_logic_vector (15 downto 0);
signal PHFSM_outputs : std_logic_vector(9 downto 1);
signal x1 : std_logic;
signal x2 : std_logic;
signal x3 : std_logic;

2. signal x4 : std_logic;
signal x5 : std_logic;
signal x6 : std_logic; -- left pointer is not equal to 0
signal x7 : std_logic; -- right pointer is not equal to 0
signal operates, InvOperates : std_logic;
signal error,error1 : std_logic;
type ram_type is array (0 to RAM_words-1) of std_logic_vector (RAM_data+2*RAM_address_size-1 downto 0);
type rom_type is array (0 to ROM_words-1) of std_logic_vector (7 downto 0);
--constant ROM : rom_type :=
-- (" "," "," ", ,14,9,7,13,9,37,2,7,8,17,21
-- " "," "," ",
-- " "," "," ", -- changes in generic
-- " "," "," "); -- ROM_words : integer := 12;
-- " "," "," ",
-- " "," "," ", ,14,9,7,13,9,37,2,7,8,17,21
-- " "," "," ",
-- " "," "," ", -- changes in generic
-- " "," "," ",
-- " "," "," ", ,14,9,7,13,9,37,2,7,8,17,21
-- " "," "," ",
-- " "," "); ROM_words : integer := 32;
constant ROM : rom_type :=
(" "," "," ", ,50,15,53,51,52,55,58,57,40,43,45
" "," "," ", ,38,39,36,22,28,29,25,21,16,17,8
" "," "," ", ,14,11,9,2,1,5,7
" "," "," ",
" "," "," ", ,14,9,7,13,9,37,2,7,8,17,21
" "," "," ",
" "," "," ", -- changes in generic
" "," "," ",
" "," "," ", ,14,9,7,13,9,37,2,7,8,17,21
" "," "," ",
" "," "); ROM_words : integer := 32;

3. signal ROM_address : integer;
signal RAM : ram_type;
signal RAM_address : integer;
signal RAM_address_previous : integer;
signal RAM_w : integer;
signal ROM_w : integer;
for local stack begin
type Lstack_memory is array(0 to Lstack_size) of std_logic_vector(RAM_address_size-1 downto 0);
signal Lstack : Lstack_memory;
signal Lstack_counter : integer range 0 to Lstack_size;
for local stack end
for output stack begin
type Ostack_memory is array(0 to RAM_words) of std_logic_vector(7 downto 0);
signal Ostack : Ostack_memory;
signal Ostack_counter : integer range 0 to RAM_words-1;
for output stack end
component PHFSM is
generic (stack_size : integer := 15);
port ( clk : in std_logic;
rst : in std_logic;
error : buffer std_logic;
X1_from_datapath : in std_logic;
X2_from_datapath : in std_logic;
X3_from_datapath : in std_logic;
X4_from_datapath : in std_logic;
X5_from_datapath : in std_logic;
X6_from_datapath : in std_logic; -- left pointer is not equal to 0
X7_from_datapath : in std_logic; -- right pointer is not equal to 0
operates : out std_logic;
outputs_to_datapath : out std_logic_vector(9 downto 1));
end component;

4. signal div1 : std_logic_vector(2 downto 0);
signal VGAstate : integer range 0 to StateMaxValue;
signal line, line_local : integer range 0 to 39;
signal column, column_local : integer range 0 to 79;
signal ASCII_local : std_logic_vector(7 downto 0);
begin
div1<= div1 + 1 when rising_edge(clkVGA);
clk <= div1(2);
process (clk,rst)
variable last_address : integer;
if rst = '1' then RAM_address <= 0;
ROM_address <= 1;
RAM_w <= 0;
ROM_w <= ROM_words;
RAM(0)(23 downto 16) <= ROM(0)(7 downto 0);
RAM(0)(15 downto 0) <= (others => '1');
LStack(0) <= (others => '0');
Lstack_counter <= 0;
Ostack_counter <= 0;
x1 <= '1';
error <= '0';
elsif falling_edge(clk) then
if RAM_address > RAM_words-1 then x1 <= '0';
else x1 <= '1';
end if;
if ROM(ROM_address) = RAM(RAM_address)(RAM_data+2*RAM_address_size-1 downto 2*RAM_address_size) then x2 <= '0';
else x2 <= '1';
if RAM_address = 255 then x3 <= '1'; -- ATTENTION WITH VALUE 255
else x3 <= '0'; end if;

5. if ROM(ROM_address) < RAM(RAM_address)(RAM_data+2
if ROM(ROM_address) < RAM(RAM_address)(RAM_data+2*RAM_address_size-1 downto 2*RAM_address_size) then x4 <= '1';
else x4 <= '0';
end if;
if ROM_address = ROM_w then x5 <= '1';
else x5 <= '0';
if Lstack_counter > Lstack_size-1 then error <= '1';
if PHFSM_outputs(1) = '1' then Lstack_counter <= Lstack_counter + 1;
Lstack(Lstack_counter) <= conv_std_logic_vector(RAM_address,RAM_address_size);
if PHFSM_outputs(2) = '1' then
RAM_address <= conv_integer(RAM(RAM_address)(RAM_address_size-1 downto 0));
if PHFSM_outputs(3) = '1' then Ostack_counter <= Ostack_counter + 1;
Ostack(Ostack_counter) <= RAM(RAM_address)(RAM_data+2*RAM_address_size-1 downto 2*RAM_address_size);
if PHFSM_outputs(4) = '1' then
RAM_address <= conv_integer(RAM(RAM_address)(2*RAM_address_size-1 downto RAM_address_size));
if PHFSM_outputs(5) = '1' then
if Lstack_counter > 0 then Lstack_counter <= Lstack_counter - 1;
RAM_address <= conv_integer(Lstack(Lstack_counter - 1));
if PHFSM_outputs(6) = '1' then RAM(RAM_address)(RAM_address_size-1 downto 0) <= Lstack(Lstack_counter+1);
if PHFSM_outputs(7) = '1' then RAM(RAM_address)(2*RAM_address_size-1 downto RAM_address_size) <= Lstack(Lstack_counter+1);
if PHFSM_outputs(8) = '1' then RAM(RAM_w+1)(RAM_data+2*RAM_address_size-1 downto 2*RAM_address_size) <= ROM(ROM_address);
RAM(RAM_w+1)(2*RAM_address_size-1 downto 0) <= (others => '1');
ROM_address <= ROM_address+1;
RAM_w <= RAM_w+1;
Lstack(Lstack_counter) <= conv_std_logic_vector(RAM_w+1,RAM_address_size);

6. if PHFSM_outputs(9) = '1' then ROM_address <= ROM_address+1;
Lstack(Lstack_counter) <= conv_std_logic_vector(RAM_address,RAM_address_size);
end if;
end process;
MyPHFSM : PHFSM port map ( clk , rst, error1 , x1, x2, x3, x4, x5, x6, x7, operates, PHFSM_outputs);
process(clk, rst)
begin
if rst = '1' then VGAstate <= 0;
elsif falling_edge(clk) then
if VGAstate=StateMaxValue then VGAstate<=0; else VGAstate<= VGAstate + 1; end if;
if rst= '1' then null;
elsif rising_edge(clk) then
case VGAstate is
when 1 to 32 => line_local <= 2;
column_local <= 2 + (VGAstate-1)*3;
ASCII_local <= "0011" & Ostack(VGAstate-1)(7 downto 4);
when 33 to 64 => line_local <= 2;
column_local <= 3 + (VGAstate-33)*3;
ASCII_local <= "0011" & Ostack(VGAstate-33)(3 downto 0);
when 65 to 96 => line_local <= 4;
column_local <= 2 + (VGAstate-65)*3;
ASCII_local <= "0011" & ROM(VGAstate-65)(7 downto 4);
when 97 to 128 => line_local <= 4;
column_local <= 3 + (VGAstate-97)*3;
ASCII_local <= "0011" & ROM(VGAstate-97)(3 downto 0);
when others => null;
end case;

7. WE_out <= '1';
ASCII_out <= ASCII_local;
column <= column_local;
line <= line_local;
Address_out <= conv_std_logic_vector((line*NumberOfColumns + column),AddressBits);
end Behavioral;