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CMPE 4784 1 picture of Tianhe, the most powerful computer in the world in Nov-2010 CMPE 478 Parallel Processing.

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Presentation on theme: "CMPE 4784 1 picture of Tianhe, the most powerful computer in the world in Nov-2010 CMPE 478 Parallel Processing."— Presentation transcript:

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2 CMPE picture of Tianhe, the most powerful computer in the world in Nov-2010 CMPE 478 Parallel Processing

3 CMPE Von Neumann Architecture CPU RAM Device sequential computer BUS

4 CMPE Memory Hierarchy Registers Cache Real Memory Disk CD Fast Slow

5 CMPE History of Computer Architecture 4 Generations (identified by logic technology) 1.Tubes 2.Transistors 3.Integrated Circuits 4.VLSI (very large scale integration)

6 CMPE PERFORMANCE TRENDS

7 CMPE PERFORMANCE TRENDS Traditional mainframe/supercomputer performance 25% increase per year But … microprocessor performance 50% increase per year since mid 80’s.

8 CMPE Moore’s Law “Transistor density doubles every 18 months” Moore is co-founder of Intel. 60 % increase per year Exponential growth PC costs decline. PCs are building bricks of all future systems. Intel 62 core xeon Phi billion

9 CMPE VLSI Generation

10 CMPE Bit Level Parallelism (upto mid 80’s) 4 bit microprocessors replaced by 8 bit, 16 bit, 32 bit etc. doubling the width of the datapath reduces the number of cycles required to perform a full 32-bit operation mid 80’s reap benefits of this kind of parallelism (full 32- bit word operations combined with the use of caches)

11 CMPE Instruction Level Parallelism (mid 80’s to mid 90’s) Basic steps in instruction processing (instruction decode, integer arithmetic, address calculations, could be performed in a single cycle) Pipelined instruction processing Reduced instruction set (RISC) Superscalar execution Branch prediction

12 CMPE Thread/Process Level Parallelism (mid 90’s to present) On average control transfers occur roughly once in five instructions, so exploiting instruction level parallelism at a larger scale is not possible Use multiple independent “threads” or processes Concurrently running threads, processes

13 CMPE Evolution of the Infrastructure Electronic Accounting Machine Era: General Purpose Mainframe and Minicomputer Era: Present Personal Computer Era: 1981 – Present Client/Server Era: 1983 – Present Enterprise Internet Computing Era: Present

14 CMPE Sequential vs Parallel Processing physical limits reached easy to program expensive supercomputers “raw” power unlimited more memory, multiple cache made up of COTS, so cheap difficult to program

15 CMPE What is Multi-Core Programming ? Answer: It is basically parallel programming on a single computer box (e.g. a desktop, a notebook, a blade)

16 CMPE Another Important Benefit of Multi-Core : Reduced Energy Consumption 2 GHz 1 GHz Single core Dual core Energy per cycle(E ) = C*Vdd Energy=E * N Energy per cycle(E’ ) = C*(0.5*Vdd) = 0.25*C*Vdd Energy’ = 2*(E’ * 0.5 * N ) = E’ * N = 0.25*(E * N) = 0.25*Energy c c c c c c Single core executes workload of N Clock cycles Each core executes workload of N/2 Clock cycles

17 CMPE SPMD Model (Single Program Multiple Data) Each processor executes the same program asynchronously Synchronization takes place only when processors need to exchange data SPMD is extension of SIMD (relax synchronized instruction execution) SPMD is restriction of MIMD (use only one source/object)

18 CMPE Parallel Processing Terminology Embarassingly Parallel: -applications which are trivial to parallelize -large amounts of independent computation -Little communication Data Parallelism: -model of parallel computing in which a single operation can be applied to all data elements simultaneously -amenable to SIMD or SPMD style of computation Control Parallelism: -many different operations may be executed concurrently -require MIMD/SPMD style of computation

19 CMPE Parallel Processing Terminology Scalability: -If the size of problem is increased, number of processors that can be effectively used can be increased (i.e. there is no limit on parallelism). -Cost of scalable algorithm grows slowly as input size and the number of processors are increased. - Data parallel algorithms are more scalable than control parallel alorithms Granularity: -fine grain machines: employ massive number of weak processors each with small memory -coarse grain machines: smaller number of powerful processors each with large amounts of memory

20 CMPE Models of Parallel Computers 1. Message Passing Model - Distributed memory - Multicomputer 2. Shared Memory Model - Multiprocessor - Multi-core 3. Theoretical Model - PRAM New architectures: combination of 1 and 2.

21 CMPE Theoretical PRAM Model Used by parallel algorithm designers Algorithm designers do not want to worry about low level details: They want to concentrate on algorithmic details Extends classic RAM model Consist of : – Control unit (common clock), synchronous – Global shared memory – Unbounded set of processors, each with its private own memory

22 CMPE Theoretical PRAM Model Some characteristics – Each processor has a unique identifier, mypid=0,1,2,… – All processors operate synhronously under the control of a common clock – In each unit of time, each procesor is allowed to execute an instruction or stay idle

23 CMPE Various PRAM Models weakest strongest EREW (exlusive read / exclusive write) CREW (concurrent read / exclusive write) CRCW (concurrent read / concurrent write) Common (must write the same value) Arbitrary (one processor is chosen arbitrarily) Priority (processor with the lowest index writes) (how write conflicts to the same memory location are handled)

24 CMPE Flynn’s Taxonomy classifies computer architectures according to: 1.Number of instruction streams it can process at a time 2.Number of data elements on which it can operate simultaneously Data Streams Single Multiple Single Multiple Instruction Streams SISD SIMD MIMD MISD

25 CMPE Shared Memory Machines Shared Address Space process (thread) process (thread) process (thread) process (thread) process (thread) Memory is globally shared, therefore processes (threads) see single address space Coordination of accesses to locations done by use of locks provided by thread libraries Example Machines: Sequent, Alliant, SUN Ultra, Dual/Quad Board Pentium PC Example Thread Libraries: POSIX threads, Linux threads.

26 CMPE Shared Memory Machines can be classified as: -UMA: uniform memory access -NUMA: nonuniform memory access based on the amount of time a processor takes to access local and global memory. Inter- connection network/ or BUS Inter- connection network Inter- connection network P.. P M.. M P M P M.. P M P M P M.. P M.. M (a) (b) (c)

27 CMPE Distributed Memory Machines Network process M M M M M Each processor has its own local memory (not directly accessible by others) Processors communicate by passing messages to each other Example Machines: IBM SP2, Intel Paragon, COWs (cluster of workstations) Example Message Passing Libraries: PVM, MPI

28 CMPE Beowulf Clusters Use COTS, ordinary PCs and networking equipment Has the best price/performance ratio PC cluster

29 CMPE Multi-Core Computing A multi-core microprocessor is one which combines two or more independent processors into a single package, often a single integrated circuit. A dual-core device contains only two independent microprocessors.

30 CMPE Comparison of Different Architectures CPU State Cache Execution unit Single Core Architecture

31 CMPE Comparison of Different Architectures CPU State Cache Execution unit Multiprocessor CPU State Cache Execution unit

32 CMPE Comparison of Different Architectures CPU State Cache Execution unit Hyper-Threading Technology CPU State

33 CMPE Comparison of Different Architectures CPU State Cache Execution unit Multi-Core Architecture CPU State Cache Execution unit

34 CMPE Comparison of Different Architectures CPU State Execution unit Multi-Core Architecture with Shared Cache CPU State Cache Execution unit

35 CMPE Comparison of Different Architectures Multi-Core with Hyper-Threading Technology CPU State Cache Execution unit CPU State Cache Execution unit CPU State

36 CMPE

37 CMPE Top 500 Most Power Supercomputer Lists ……..

38 CMPE Grid Computing provide access to computing power and various resources just like accessing electrical power from electrical grid Allows coupling of geographically distributed resources Provide inexpensive access to resources irrespective of their physical location or access point Internet & dedicated networks can be used to interconnect distributed computational resources and present them as a single unified resource Resources: supercomputers, clusters, storage systems, data resources, special devices

39 CMPE Grid Computing the GRID is, in effect, a set of software tools, which when combined with hardware, would let users tap processing power off the Internet as easily as the electrical power can be drawn from the electricty grid. Examples of Grids: -TeraGrid (USA) -EGEE Grid (Europe) -TR-Grid (Turkey)

40 CMPE 4784 GRID COMPUTING Power Grid Compute Grid

41 CMPE Archeology Astronomy Astrophysics Civil Protection Comp. Chemistry Earth Sciences Finance Fusion Geophysics High Energy Physics Life Sciences Multimedia Material Sciences … >250 sites 48 countries >50,000 CPUs >20 PetaBytes >10,000 users >150 VOs >150,000 jobs/day

42 CMPE Virtualization Virtualization is abstraction of computer resources. Make a single physical resource such as a server, an operating system, an application, or storage device appear to function as multiple logical resources It may also mean making multiple physical resources such as storage devices or servers appear as a single logical resource Server virtualization enables companies to run more than one operating system at the same time on a single machine

43 CMPE Advantages of Virtualization Most servers run at just %capacity – virtualization can increase server utilization to 70% or higher. Higher utilization means fewer computers are required to process the same amount of work. Fewer machines means less power consumption. Legacy applications can also be run on older versions of an operating system Other advantages: easier administration, fault tolerancy, security

44 CMPE VMware Virtual Platform Virtual machine 1 Apps 1 OS 1 X86, motherboard disks, display, net.. Virtual machine 2 Apps 2 OS 2 X86, motherboard disks, display, net.. VMware Virtual Platform X86, motherboard, disks, display, net.. Virtual machines Real machines VMware is now tens of billion dollar company !!

45 CMPE Cloud Computing Style of computing in which IT-related capabilities are provided “as aas a service service”,allowing users to access technology-enabled services from the InternetInternet ("in the cloud") without knowledge of, expertise with, or control over the technology infrastructure that supports them. General concept that incorporates software as a service (SaaS), Web 2.0 andsoftware as a serviceWeb 2.0 other recent, well-known technology trends, in which the common theme is reliance on the Internet for satisfying the computing needs of the users.

46 CMPE 4784 Cloud Computing Virtualisation provides separation between infrastructure and user runtime environment Users specify virtual images as their deployment building blocks Pay-as-you-go allows users to use the service when they want and only pay for what they use Elasticity of the cloud allows users to start simple and explore more complex deployment over time Simple interface allows easy integration with existing systems 45

47 CMPE 4784 Cloud: Unique Features Ease of use – REST and HTTP(S) Runtime environment – Hardware virtualisation – Gives users full control Elasticity – Pay-as-you-go – Cloud providers can buy hardware faster than you! 46

48 CMPE 4784 Example Cloud: Amazon Web Services EC2 (Elastic Computing Cloud) is the computing service of Amazon – Based on hardware virtualisation – Users request virtual machine instances, pointing to an image (public or private) stored in S3 – Users have full control over each instance (e.g. access as root, if required) – Requests can be issued via SOAP and REST 47

49 CMPE 4784 Example Cloud: Amazon Web Services Pricing information 48

50 CMPE 4784 PARALLEL PERFORMANCE MODELS and ALGORITHMS 49

51 CMPE Amdahl’s Law The serial percentage of a program is fixed. So speed-up obtained by employing parallel processing is bounded. Lead to pessimism in in the parallel processing community and prevented development of parallel machines for a long time. Speedup = 1 s + 1-s P In the limit: Spedup = 1/s s

52 CMPE Gustafson’s Law Serial percentage is dependent on the number of processors/input. Demonstrated achieving more than 1000 fold speedup using 1024 processors. Justified parallel processing

53 CMPE Algorithmic Performance Parameters Notation Input size Time Complexity of the best sequential algorithm Number of processors Time complexity of the parallel algorithm when run on P processors Time complexity of the parallel algorithm when run on 1 processors

54 CMPE Algorithmic Performance Parameters Speed-Up Efficiency

55 CMPE Algorithmic Performance Parameters Work = Processors X Time – Informally: How much time a parallel algorithm will take to simulate on a serial machine – Formally:

56 CMPE Algorithmic Performance Parameters Work Efficient: – Informally: a work efficient parallel algorithm does no more work than the best serial algorithm – Formally: a work efficient algorithm satisfies:

57 CMPE Algorithmic Performance Parameters Scalability: – Informally, scalability implies that if the size of the problem is increased, the number of processors effectively used can be increased (i.e. there is no limit on parallelism) – Formally, scalability means:

58 CMPE Algorithmic Performance Parameters Some remarks: – Cost of scalable algorithm grows slowly as input size and the number of procesors are increased – Level of ‘control parallelism’ is usually a constant independent of problem size – Level of ‘data parallelism’ is an increasing function of problem size – Data parallel algorithms are more scalable than control parallel algorithms

59 CMPE Goals in Designing Parallel Algorithms Scalability: – Algorithm cost grows slowly, preferably in a polylogarithmic manner Work Efficient: – We do not want to waste CPU cycles – May be an important point when we are worried about power consumption or ‘money’ paid for CPU usage

60 CMPE 4784 Array of N numbers can be summed in log(N) steps using Summing N numbers in Parallel x1 x2 x3 x4 x5 x6 x7 x8 x1+x2 x2 x3+x4 x4 x5+x6 x6 x7+x8 x8 x1+..+x4 x2 x3+x4 x4 x5+..+x8 x6 x7+x8 x8 x1+..+x8 x2 x3+x4 x4 x5+..+x8 x6 x7+x8 x8 step 1 step 2 step 3 result N/2 processors

61 CMPE 4784 Prefix Summing N numbers in Parallel x1 x2 x3 x4 x5 x6 x7 x8 x1+x2 x2+x3 x3+x4 x4+x5 x5+x6 x6+x7 x7+x8 x8 x1+..+x4 x2+..+x4 x3+..+x6 x4+..+x7 x5+..+x8 x6+..+x8 x7+x8 x8 x1+..+x8x2+..+x8 x3+..+x8 x4+..+x8 x5+..+x8 x6+..+x8 x7+x8 x8 step 1 step 2 step 3 Computing partial sums of an array of N numbers can be done in log(N) steps using N processors

62 CMPE 4784 Prefix Paradigm for Parallel Algorithm Design Prefix computation forms a paradigm for parallel algorithm development, just like other well known paradigms such as: – divide and conquer, dynamic programming, etc. Prefix Paradigm: – If possible, transform your problem to prefix type computation – Apply the efficient logarithmic prefix computation Examples of Problems solved by Prefix Paradigm: – Solving linear recurrence equations – Tridiagonal Solver – Problems on trees – Adaptive triangular mesh refinement

63 CMPE 4784 Solving Linear Recurrence Equations Given the linear recurrence equation: we can rewrite it as: if we expand it, we get the solution in terms of partial products of coefficients and the initial values z 1 and z 0 : use prefix to compute partial products

64 CMPE 4784 Pointer Jumping Technique A linked list of N numbers can be prefix-summed in log(N) steps using N processors step 1 step 3 x1 x2 x3 x4 x5 x6 x7 x8 x1+..+x4 x2+..+x5 x3+..+x6 x4+..+x7 x5+..+x8 x6+x7 x7+x8 x8 step 2 x1+.x2 x2+x3 x3+x4 x4+x5 x5+x6 x6+x7 x7+x8 x8 x1+..+x8 x2+..+x8 x3+..+x8 x4+..+x8 x5+..+x8 x6+..+x8 x7+x8 x8

65 CMPE 4784 Euler Tour Technique b d a c fge hi Tree Problems: Preorder numbering Postorder numbering Number of Descendants Level of each node To solve such problems, first transform the tree by linearizing it into a linked-list and then apply the prefix computation

66 CMPE 4784 Computing Level of Each Node by Euler Tour Technique b d a c fge hi weight assignment: 1 level(v) = pw( ) level(root) = 0 w( ) pw( ) i g b a d a c a g h g bf b e b a initial weights: prefix:

67 CMPE 4784 Computing Number of Descendants by Euler Tour Technique b d a c fge hi weight assignment: 01 # of descendants(v) = pw( ) - pw( ) # of descendants(root) = n w( ) pw( ) i g b a d a c a g h g bf b e b a initial weights: prefix:

68 CMPE 4784 Preorder Numbering by Euler Tour Technique b d a c fge hi weight assignment: 10 preorder(v) = 1 + pw( ) preorder(root) = 1 w( ) pw( ) i g b a d a c a g h g bf b e b a initial weights: prefix:

69 CMPE 4784 Postorder Numbering by Euler Tour Technique b d a c fge hi weight assignment: 01 postorder(v) = pw( ) postorder(root) = n w( ) pw( ) i g b a d a c a g h g bf b e b a initial weights: prefix:

70 CMPE 4784 Binary Tree Traversal Preorder Inorder Postorder

71 CMPE 4784 Brent’s Theorem Given a parallel algorithm with computation time D, if parallel algorithm performs W operations then P processors can execute the algorithm in time D + (W-D)/P For proof: consider DAG representation of computation

72 CMPE 4784 Work Efficiency Parallel Summation Parallel Prefix Summation

73 CMPE 4784 Work Efficiency Parallel Summation Parallel Prefix Summation


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