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1 n Memory market and memory complexity n Notation n Faults and failures n MATS+ March Test n Memory fault models n March test algorithms n Inductive fault.

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Presentation on theme: "1 n Memory market and memory complexity n Notation n Faults and failures n MATS+ March Test n Memory fault models n March test algorithms n Inductive fault."— Presentation transcript:

1 1 n Memory market and memory complexity n Notation n Faults and failures n MATS+ March Test n Memory fault models n March test algorithms n Inductive fault analysis n Summary Lecture 15 Memory Test Original slides copyright by Mike Bushnell and Vishwani Agrawal

2 2 Density and Cost Trends n DRAM Invention (Intel) 1024 bits n st 256 Mb DRAM papers n st 256 Mb DRAM samples 1 cent/bit --> 120 X cent/bit n Kilburn -- Ferranti Atlas computer (Manchester Univ.) -- Invented Virtual Memory n IBM 360/85 - cache memory (to hide slow core) n Cache DRAM -- SRAM cache + DRAM now on 1 chip ¢ ¢

3 3 Memory Cells Per Chip

4 4 Test Time in Seconds (Memory Size - n Bits) n 1 Mb 4 Mb 16 Mb 64 Mb 256 Mb 1 Gb 2 Gb n n X log 2 n n 3/ hr 9.2 hr 73.3 hr hr hr n hr hr hr hr hr hr hr Size Number of Test Algorithm Operations

5 5 Notation n 0 -- A cell is in logical state 0 n 1 -- A cell is in logical state 1 n X -- A cell is in logical state X n A -- A memory address n ABF -- AND Bridging Fault n AF -- Address Decoder Fault n B -- Memory # bits in a word n BF -- Bridging Fault n C -- A Memory Cell n CF -- Coupling Fault

6 6 Notation (Continued) n CFdyn -- Dynamic Coupling Fault n CFid -- Idempotent Coupling Fault n CFin -- Inversion Coupling Fault n coupling cell – cell whose change causes another cell to change n coupled cell – cell forced to change by a coupling cell n DRF -- RAM Data Retention Fault n k -- Size of a neighborhood n M -- memory cells, words, or address set n n -- # of Memory bits n N -- Number of address bits: n = 2 N n NPSF -- Neighborhood Pattern Sensitive Fault

7 7 Notation (Continued) n OBF -- OR Bridging Fault n SAF -- Stuck-at Fault n SCF -- State Coupling Fault n SOAF -- Stuck-Open Address Decoder Fault n TF -- Transition Fault

8 8 Faults n System -- Mixed electronic, electromechanical, chemical, and photonic system (MEMS technology) n Failure -- Incorrect or interrupted system behavior n Error -- Manifestation of fault in system n Fault -- Physical difference between good & bad system behavior

9 9 Fault Types n Fault types: Permanent -- System is broken and stays broken the same way indefinitely Transient -- Fault temporarily affects the system behavior, and then the system reverts to the good machine -- time dependency, caused by environmental condition Intermittent -- Sometimes causes a failure, sometimes does not

10 10 Failure Mechanisms n Permanent faults: Missing/Added Electrical Connection Broken Component (IC mask defect or silicon-to-metal connection) Burnt-out Chip Wire Corroded connection between chip & package Chip logic error (Pentium division bug)

11 11 Failure Mechanisms (Continued) n Transient Faults: Cosmic Ray   particle (ionized Helium atom) Air pollution (causes wire short/open) Humidity (temporary short) Temperature (temporary logic error) Pressure (temporary wire open/short) Vibration (temporary wire open) Power Supply Fluctuation (logic error) Electromagnetic Interference (coupling) Static Electrical Discharge (change state) Ground Loop (misinterpreted logic value)

12 12 Failure Mechanisms (Continued) n Intermittent Faults: Loose Connections Aging Components (changed logic delays) Hazards and Races in critical timing paths (bad design) Resistor, Capacitor, Inductor variances (timing faults) Physical Irregularities (narrow wire -- high resistance) Electrical Noise (memory state changes)

13 13 Physical Failure Mechanisms n Corrosion n Electromigration n Bonding Deterioration -- Au package wires interdiffuse with Al chip pads n Ionic Contamination -- Na + diffuses through package and into FET gate oxide n Alloying -- Al migrates from metal layers into Si substrate n Radiation and Cosmic Rays -- 8 MeV, collides with Si lattice, generates n - p pairs, causes soft memory error

14 14 Memory Test Levels Chip, Array, & Board

15 15 March Test Notation n r -- Read a memory location n w -- Write a memory location n r0 -- Read a 0 from a memory location n r1 -- Read a 1 from a memory location n w0 -- Write a 0 to a memory location n w1 -- Write a 1 to a memory location n -- Write a 1 to a cell containing 0 n -- Write a 0 to a cell containing 1

16 16 March Test Notation (Continued) n -- Complement the cell contents n -- Increasing memory addressing n -- Decreasing memory addressing n -- Either increasing or decreasing

17 17 More March Test Notation n -- Any write operation n -- Denotes a particular fault,... n -- I is the fault sensitizing condition, F is the faulty cell value n -- Denotes a fault covering n cells I1,..., In-1 are fault sensitization conditions in cells 1 through n - 1 for cell n In gives sensitization condition for cell n If In is empty, write In / F as F A

18 18 MATS+ March Test M0: { March element (w0) } for cell := 0 to n - 1 (or any other order) do write 0 to A [cell]; M1: { March element (r0, w1) } for cell := 0 to n - 1 do read A [cell]; { Expected value = 0} write 1 to A [cell]; M2: {March element (r1, w0) } for cell := n – 1 down to 0 do read A [cell]; { Expected value = 1 } write 0 to A [cell];

19 19 Fault Modeling n Behavioral (black-box) Model -- State machine modeling all memory content combinations -- Intractable n Functional (gray-box) Model -- Used n Logic Gate Model -- Not used Inadequately models transistors & capacitors n Electrical Model -- Very expensive n Geometrical Model -- Layout Model Used with Inductive Fault Analysis

20 20 Functional Model

21 21 Simplified Functional Model

22 22 Reduced Functional Model (van de Goor) n n Memory bits, B bits/word, n/B addresses n Access happens when Address Latch contents change n Low-order address bits operate column decoder, high-order operate row decoder n read -- Precharge bit lines, then activate row n write -- Keep driving bit lines during evaluation n Refresh -- Read all bits in 1 row and simultaneously refresh them

23 23 Subset Functional Faults abcdefghabcdefgh Functional fault Cell stuck Driver stuck Read/write line stuck Chip-select line stuck Data line stuck Open circuit in data line Short circuit between data lines Crosstalk between data lines

24 24 Subset Functional Faults (Continued) ijklmnopijklmnop Functional fault Address line stuck Open circuit in address line Shorts between address lines Open circuit in decoder Wrong address access Multiple simultaneous address access Cell can be set to 0 but not to 1 (or vice versa) Pattern sensitive cell interaction

25 25 Reduced Functional Faults SAF TF CF NPSF Fault Stuck-at fault Transition fault Coupling fault Neighborhood Pattern Sensitive fault

26 26 Stuck-at Faults n Condition: For each cell, must read a 0 and a 1. n ( ) AA

27 27 Transition Faults n Cell fails to make 0 1 or 1 0 transition n Condition: Each cell must undergo a transition and a transition, and be read after such, before undergoing any further transitions. n, transition fault

28 28 Coupling Faults n Coupling Fault (CF): Transition in bit j causes unwanted change in bit i n 2-Coupling Fault: Involves 2 cells, special case of k-Coupling Fault Must restrict k cells to make practical n Inversion and Idempotent CFs -- special cases of 2-Coupling Faults n Bridging and State Coupling Faults involve any # of cells, caused by logic level n Dynamic Coupling Fault (CFdyn) -- Read or write on j forces i to 0 or 1

29 29 Inversion Coupling Faults (CFin) n or in cell j inverts contents of cell i n Condition: For all cells that are coupled, each should be read after a series of possible CFins may have occurred, and the # of coupled cell transitions must be odd (to prevent the CFins from masking each other). n and

30 30 Good Machine State Transition Diagram

31 31 CFin State Transition Diagram

32 32 Idempotent Coupling Faults (CFid) n or transition in j sets cell i to 0 or 1 n Condition: For all coupled faults, each should be read after a series of possible CFids may have happened, such that the sensitized CFids do not mask each other. n Asymmetric: coupled cell only does or n Symmetric: coupled cell does both due to fault n,,,

33 33 CFid Example

34 34 Dynamic Coupling Faults (CFdyn) n Read or write in cell of 1 word forces cell in different word to 0 or 1 n,,, and | Denotes “OR” of two operations n More general than CFid, because a CFdyn can be sensitized by any read or write operation

35 35 Bridging Faults n Short circuit between 2+ cells or lines n 0 or 1 state of coupling cell, rather than coupling cell transition, causes coupled cell change n Bidirectional fault -- i affects j, j affects i n AND Bridging Faults (ABF):,,, n OR Bridging Faults (OBF):,,,

36 36 State Coupling Faults n Coupling cell / line j is in a given state y that forces coupled cell / line i into state x n,,,

37 37 Address Decoder Faults (ADFs) n Address decoding error assumptions: Decoder does not become sequential Same behavior during both read & write n Multiple ADFs must be tested for n Decoders have CMOS stuck-open faults

38 38 Theorem 9.2 n A March test satisfying conditions 1 & 2 detects all address decoder faults. n... Means any # of read or write operations n Before condition 1, must have wx element x can be 0 or 1, but must be consistent in test Condition 1 2 March element (rx, …, w x )

39 39 Proof Illustration

40 40 Necessity Proof n Removing rx from Condition 1 prevents A or B fault detection when x read n Removing rx from Condition 2 prevents A or B fault detection when x read n Removing rx or wx from Condition 1 misses fault D2 n Removing rx or wx from condition 2 misses fault D3 n Removing both writes misses faults C and D1

41 41 Sufficiency Proof n Faults A and B: Detected by SAF test n Fault C: Initialize memory to h (x or x). Subsequent March element that reads h and writes h detects Fault C. Marching writes h to A v. Detection: read A w Marching writes h to A z. Detection: read A y n Fault D: Memory returns random result when multiple cells read simultaneously. Generate fault by writing A x, Detection: read A w or A y ( or marches)

42 42 Reduced Functional Faults Fault SAF CF AF TF NPSF abcdefghijklmnopabcdefghijklmnop Functional fault Cell stuck Driver stuck Read/write line stuck Chip-select line stuck Data line stuck Open circuit in data line Short circuit between data lines Crosstalk between data lines Address line stuck Open circuit in address line Shorts between address lines Open circuit in decoder Wrong address access Multiple simultaneous address access Cell can be set to 0 (1) but not to 1 (0) Pattern sensitive cell interaction

43 43 Fault Modeling Example 1 SCF SA0 SCF AF+SAF SAF SA0 TF

44 44 Fault Modeling Example 2 ABF SA0 ABF SA1 SA1+SCF SCF gg

45 45 Multiple Fault Models n Coupling Faults: In real manufacturing, any # can occur simultaneously n Linkage: A fault influences behavior of another n Example March test that fails: { (w0) ; (r0, w1); (w0, w1); (r1)} Works only when faults not linked

46 46 Fault Hierarchy

47 47 Tests for Linked AFs n Cases 1, 2, 3 & 5 -- Unlinked n Cases 4 & 6 -- Linked

48 48 DRAM/SRAM Fault Modeling DRAM or SRAM Faults Shorts & opens in memory cell array Shorts & opens in address decoder Access time failures in address decoder Coupling capacitances between cells Bit line shorted to word line Transistor gate shorted to channel Transistor stuck-open fault Pattern sensitive fault Diode-connected transistor 2 cell short Open transistor drain Gate oxide short Bridging fault Model SAF,SCF AF Functional CF IDDQ SOF PSF

49 49 SRAM Only Fault Modeling Faults found only in SRAM Open-circuited pull-up device Excessive bit line coupling capacitance Model DRF CF

50 50 DRAM Only Fault Modeling Faults only in DRAM Data retention fault (sleeping sickness) Refresh line stuck-at fault Bit-line voltage imbalance fault Coupling between word and bit line Single-ended bit-line voltage shift Precharge and decoder clock overlap Model DRF SAF PSF CF PSF AF

51 51 Test Influence on SRAM Fault Coverage

52 52 Influence of Addressing Order on Fault Coverage

53 53 Critical Path Length n Length of parallel wires separated by dimension of spot defect size n TFs and CFids happen only on long wires Fault class Stuck-at Stuck-open Transition State Coup. Idemp. Coup. Data retention Total < < < < < <2 51.3% 21.0% 0% 9.9% 0% 17.8% 100% <9 49.8% 11.9% 7.0% 13.2% 3.3% 14.8% 100% Spot defect size (  m)

54 54 Fault Frequency n Obtained with Scanning Electron Microscope n CFin and TF faults rarely occurred Cluster # Devices Fault class Stuck-at and Total failure Stuck-open Idempotent coupling State coupling ? Data retention ?

55 55 Functional RAM Testing with March Tests n March Tests can detect AFs -- NPSF Tests Cannot n Conditions for AF detection: Need ( r x, w x) n In the following March tests, addressing orders can be interchanged

56 56 Irredundant March Tests Algorithm MATS MATS+ MATS++ MARCH X MARCH C— MARCH A MARCH Y MARCH B Description { (w0); (r0, w1); (r1) } { (w0); (r0, w1); (r1, w0) } { (w0); (r0, w1); (r1, w0, r0) } { (w0); (r0, w1); (r1, w0); (r0) } { (w0); (r0, w1); (r1, w0); (r0, w1); (r1, w0); (r0) } { (w0); (r0, w1, w0, w1); (r1, w0, w1); (r1, w0, w1, w0); (r0, w1, w0) } { (w0); (r0, w1, r1); (r1, w0, r0); (r0) } { (w0); (r0, w1, r1, w0, r0, w1); (r1, w0, w1); (r1, w0, w1, w0); (r0, w1, w0) }

57 57 Irredundant March Test Summary Algorithm MATS MATS+ MATS++ MARCH X MARCH C— MARCH A MARCH Y MARCH B SAF All AF Some All TF All CF in All CF id All CF dyn All SCF All Linked Faults Some

58 58 March Test Complexity Algorithm MATS MATS+ MATS++ MARCH X MARCH C— MARCH A MARCH Y MARCH B Complexity 4n 5n 6n 10n 15n 8n 17n

59 59 MATS+ Example Cell (2,1) SA0 Fault MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }

60 60 MATS+ Example Cell (2, 1) SA1 Fault MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }

61 61 MATS+ Example Multiple AF Type C n Cell (2,1) is not addressable n Address (2,1) maps into (3,1) & vice versa n Can’t write (2,1), read (2,1) gives random # MATS+: { M0: (w0); M1: (r0, w1); M2: (r1), w0 }

62 62 RAM Tests for Layout-Related Faults Inductive Fault Analysis: 1 Generate defect sizes, location, layers based on fabrication line model 2 Place defects on layout model 3 Extract defective cell schematic & electrical parameters 4 Evaluate cell testing, using VLASIC n Dekker found these faults: SAF, SOF, TF, SCF, CFid, DRF Proposed IFA-9 March test Delay means wait 100 ms

63 63 Inductive Fault Analysis March Tests Algor- ithm IFA-9 IFA-13 SAF All TF All AF All SOF All SCF All CFid All DRF All Operations 12n+Delays 16n+Delays Physical Defect Fault Coverage Algor- ithm IFA-9 IFA-13 Description { (w0); (r0, w1); (r1, w0); (r0, w1); (r1, w0); Delay; (r0, w1); Delay; (r1) } { (w0); (r0, w1, r1); (r1, w0, r0); (r0, w1, r1), (r1, w0, r0), Delay; (r0, w1); Delay; (r1) }

64 64 IFA Test Validation n Higher scores show better tests Test MATS+ MATS+ and Delay March C March C and Delay IFA-9 and Delay IFA-13 IFA-13 and Delay Score Test Time 5n 8n + 2 Delay 11n 14n + 2 Delay 12n + 2 Delay 13n 16n + 2 Delay

65 65 Memory Testing Summary n Multiple fault models are essential n Combination of tests is essential: March – SRAM and DRAM NPSF -- DRAM DC Parametric -- Both AC Parametric -- Both n Inductive Fault Analysis is now required


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