Presentation on theme: "Analysis of Power Management in Embedded Systems David Souders, Mengesha Tekle EEL 6935."— Presentation transcript:
Analysis of Power Management in Embedded Systems David Souders, Mengesha Tekle EEL 6935
Table of Contents 1. Introduction 2. Energy/Power Breakdown of Pipelined NM Caches 3. Low Power Light-Weight Embedded Systems 4. Design and Power Management of Energy Harvesting systems 5. Conclusion
Introduction Customer driven metrics. Smaller/lighter devices became mobile. Power management increasing issue for designer. The focus of this presentation is to examine this power problem and its solutions.
Customer Driven Constraints
Energy/Power Breakdown of Pipelined Nanometer Caches Samuel Rodriguez and Bruce Jacob University of Maryland College Park
Research Aims Identify the sources of energy/power dissipation in a typical cache. Clarify why such power loss occurs takes place. Explore this result with respect to a pipelined cache design space. Produce a more accurate model than most popular commercial analysis systems.
Research Claims Device leakage currents becoming the dominant cause of power dissipation in nanometer caches. Effects of pipelining overhead need to be accounted for. Gate leakage could show a decreasing trend in deep nm devices.
Leakage Dynamic power dissipation. –Switching states Static power dissipation. –Device is inactive –Sub-threshold leakage –Gate leakage
Pipelined Cache Keep up with speed of microprocessor core. Race against the clock. Added transistor cell area.
Cache Analysis Implicit pipelining through wave pipelining. Not suited for high volume, high speed microprocessor caches. Process Temperature Variation (PVT) lead to delay imbalances.
Experimental Methodology More optimum circuits/topologies. Accurate model of explicit cache pipelining. More realistic model of physical transistor characteristics (e.g. parasitics). Dynamic wire modeling.
Results Larger technologies are dominated by dynamic power. As device size reduces to deep nm, static power dominates. Cache size also shows a tendency toward sub threshold leakage.
Dynamic + Static Power Despite talk of increasing gate leakage, the results show the opposite effect. –Thinner Gate Oxide –Lower supply voltages –Smaller devices Increasing cache associativity does not show an increase in power dissipation. Technology scaling can both increase and decrease cache power.
Detailed Power Breakdown As device size decreases, the decrease in power become less significant and eventually increases. Two main contributors: Bitlines, Pipelined Cache
Power Breakdown (Cont.) Power Dissipation due to bitlines increases as cache size increases. Other factors don’t show strong size dependency, they depend on implementation.
Conclusion Detailed power breakdown of different nm pipelined cache configurations. –Varying: Size, associativity, and process technology Static power will dominate smaller device sizes. Gate leakage tunneling currents do not contribute significantly to cache power loss. Using explicit pipelining can show a relatively large contribution to power loss.
Low Power, Light Weight
Low Power Light-weight Embedded Systems Majid Sarrafzadeh, Foad Dabin, Roozbeh Jafari, Tammara Massey, Ani Nahapetan UCLA, University of Texas at Dallas, and UC Berkeley
Low Power, Light Weight Challenge: energy consumption and reliability due to battery size. Advanced due to fabrication Constraints due to applications requiring low-profile, mobile and cost-effective devices.
Low Power, Light Weight Definition: low-profile, small size, unobtrusive and portable processing elements with limited power resources. Applications: sensing, processing and communications. Characteristics: limited computational capabilities, memory, speed and I/O. Networks too complex for computational power.
Low Power, Light Weight Challenges Scheduling for power management –Task scheduling most common method to lower power consumption. –Saves power by shutting down unused portions of device. Software power optimization –Code compression and coding. –Most code compression focused memory optimization. –Positive side effect: lower energy consumption because less accesses to memory; reduction memory accesses lead reduction power dissipation in bus and interconnects. Low power communication –Significant amount energy consumed on-chip interconnect and I/O buses. –Main loss voltage swings in communication lines. –Solution: bus encoding and encoding techniques used improve performance in terms throughput and latency in turn reducing voltage swings along interconnect lines.
Low Power, Light Weight Challenges Low power security –Security protocols involve complex computations and communications. –Complicated due to limited processing power, communication bandwidth, and battery size. –Due to application necessary (military sensors, company monitoring) –Researched topics: power-aware secure protocols, secure routing schemes, and data aggregation and group formation. Low power display –Backlight to displays consumes significant energy –Little research being done –Topics include low-power GUI and low-power human-computer interaction.
Low Power, Light Weight Challenges Low power data management –Uncertainty in sensor readings due environmental interference and faults in inexpensive embedded systems. –Tree-based and multi-path-based query aggregation techniques, in-network data processing. Fault tolerance and reliability –Most common approach: redundancy –Add components, add power consumption –Cannot be handled locally since may not be feasible gather info from all nodes. –Unreliability of hardware due to cost-effectiveness.
Minimum Skew Utilization Optimizing the power consumption and system lifetime by evenly distributing node utilization and communication across the network. Minimize the skew in energy consumption due to wireless communication across highly congested nodes. Definition: There exists an exponential number of paths connecting source to destination nodes. There exists a node in every path that has highest energy consumption rate.
Minimum Skew Utilization v 1 receiver; v k+2 transmitter Each of the split nodes is assigned a cost increasing from left to right. The higher k value the more accurate the solution. Cost assignments enforce the min-cost flow technique to utilize the split nodes with smaller indices first.
Minimum Skew Utilization Theorem 1: c il cost, y il amount of flow; minimize equation with error of: The cost assignment on the splits forces network to route flow from l th split, if it cannot be routed through any number of other nodes whose (l-1) th splits is empty.
Minimum Skew Utilization Theorem 2: solution minimizes difference of maximum flows across every two disjoint paths connecting source and destination node. Theorem 3: lexicographically sorted solution of minimal- skew routing is unique. Results: max traffic reduction by factor of 4 when k=4 compared to k=1 with a 20% increase in delay Future –Explore distributed version of technique. –Fast optimal or sub-optimal solution is desired for highly dynamic networks where quality of links may change. –Effect of several cost series on split nodes.
Static Voltage Scheduling Assignment of supply voltage to each module of system. Object: minimize energy consumption for given computation time and/or throughput constraints. Timing management problem. Unified formulation with linear size number of constraints in the optimization problem as opposed to exponential. How linear? –Theorem: The delay between any node and output is independent of the choice of the path taken and is unique.
Static Voltage Scheduling If P 1 is shorter than P 2, P 2 is the critical path, and the edge of P 1 can be delayed to match the critical path without violating timing constraints. Solution space convex- convex objective and convex feasible region only one optimal solution, globally optimal. All delay constraints are planes bounding solution space. Future –Extended voltage scheduling. –Develop design rules assist developers. –Effects voltage level shifters on performance and related optimization problems.
Summary Minimum Skew Utilization and Static Voltage Scaling. The change to smaller systems has driven demand for a broad spectrum applications. Question: How do you get power to systems that can’t have large batteries and are in remote locations? Answer: Energy Harvesting from the environment in and around the objects/subjects themselves.
Design and Power Management of Energy Harvesting Embedded Systems Vijay Raghunathan and Pai H. Chou NEC Labs America and University of California
Design & Power Management of Energy Harvesting ES Reduced size systems mounted or implanted more objects than ever. Automobiles own infrastructure power. Trees in remote location, no readily available supply of power. Wind, water, sun – low efficiency when small. Efficiency –Conversion: convert from one form of energy to another (light to electricity). –Transfer: from source to the supply. –Buffering: once it has been harvested. –Consumption: amount of useful work given the harvestable energy.
Design & Power Management of Energy Harvesting ES Environmentally embedded: building, habitat, greenhouse, etc... Abundant energy available harvesting. Wearable of implantable: person or animal… Energy subject itself in addition environment subject operates. Wireless energy transfer: buried or embedded into walls (inductive charging – energy from electromagnetic emissions).
Mechanisms for Energy Harvesting Harvestable energy –mechanical, thermal, photovoltaic, electromagnetic, biological, and chemical. Mechanical (most prevalent) –wind, limb movement, strain, ambient vibration, car wheel rotation, etc… Key differences in system –Output power level –AC vs. DC –Dynamic range –Impedance modeling AC power: windmills, magnetic coil generators, piezoelectric generators, and magnetic induction DC power: thermal and photovoltaic Options –Rectify current –Design self-timed circuits will run directly rectified AC power with min conversion loss. –Even DC need to obtain different voltage levels – more conversion loss.
System Design Issues Voltage and Current Need high voltage – power or charge (voltage regulators) Linear (analog/RF) vs. switching (digital) regulators Switching divided into buck, boost, buck-boost. Buck - perform voltage step-down (efficient) but input must be higher than output. Boost - voltage step-up (less efficient) Buck-boost: combination Battery: act as supplier/consumer need 2 voltage regulators
System Design Issues Voltage and Current Overall conversion efficiency dependent on operating range not just input/output. Internal power fragmentation problem –What happens when power entering system lower than conversion? Solution: use boost regulator raise voltage above threshold (less efficient). Another problem: dynamic voltage range (choose alternative cap composition, parallel vs. series).
System Design Issues Maximum Power Point Tracking Drawing power energy harvesting source at level maximizes power output. DC: When the supply and load impedance matched. AC: related resonant frequency of device along with magnitude of physical oscillation. Not standard but without consideration losses 65-90%.
How measure MPPT? Input intensity must be know either before or after electricity conversion. Ex: solar power (DC) –Determined mainly by light intensity then temperature. –If take before, then need 2 sensors, one for light and one for temperature (temp sensor inaccurate and small compared solar panels). –After- measure voltage and current levels (only works if battery or cap to power system while load disconnected). AC: power maximized rectifier voltage ½ open circuit voltage
MPPT controller Controller either hardware (before) or software (after). Hardware: autonomous, low overhead, part of power subsystem modular way without DSP/μP (optimal choice). Software: suitable higher power systems, high power consumed DSP/μP. –Disadvantages Power consumed DSP/μP More complex software Use precious I/O pins for control Inability operate lose DSP or μP
Power Defragmentation Problem: dynamic range power even with MPPT Simple solution: Add more sources Complication: cant simply add heterogeneous power sources. External power fragmentation problem –If all sources combined are not enough then all the power will be discarded. Proposal: power matching switches –Divide up system into subsystems that can be powered separately.
Energy Storage Devices Batteries current technology Alternative –Supercapacitors: commonly used buffering transient energy (store energy regenerative brake systems hybrid cars). Do not have aging and rate-capacity issues Limited energy capacity Higher leakage
Power Management Issues Harvesting Aware Power Management Adapting power management policy. –Changing environment –State of the harvesting device –Non-idealities
Energy Neutrality Conventional energy optimization metrics may not be suitable. More suitable for a harvesting network to operate in an energy neutral mode. Energy neutrality can be achieved by: –Average power generated by the harvesting device. –Capacity of energy storage device. –Design choices by system architect.
Analyzing Energy Neutrality Requirements Non-idealities to consider: –Round trip efficiency –Self discharge The theorem characterizes the sustainable performance level that can be supported in energy neutral mode. It also specifies the minimum capacity of energy storage element to achieve energy neutrality.
Other Power Management Techniques Node level power management –Adapt node performance in response to temporal variations. Network level power management –Data routes can be chosen for uniform routing load. –An increase in the network’s energy scalability.
Summary Harvesting mechanisms MPPT Power Defragmentation Energy storage devices Power Management –Node level –Network level
Conclusion Dynamic power problem. There exist many methods of increasing the efficiency of your power consumption. As products are improved, customer metrics become more stringent. Cyclical power design methodology. Embedded system design becoming more complex