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Computer Architecture & Operating Systems

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1 Computer Architecture & Operating Systems
Workshop 2 - Lecture 1 Plagiarism & Citing Sources / Program Execution, Buses & I/O Devices Last week’s workshop gave an introduction to the MScSIS programme, and an introduction to computers and discussed program execution, interrupts and instruction sets. In this first presentation of Workshop 2, we begin by defining plagiarism and the importance of correctly citing sources. We then go on to discuss the concept of a computer bus and explore how external devices are connected to a computer and can be accessed by the processor.

2 Academic Report Writing
Referencing Sources correctly Avoiding Plagiarism Throughout the MScSIS programme, you will be required to write a number of essays, reports and eventually a thesis. These can all be considered under the heading of academic report writing. It is often necessary, in the course of academic report writing, to conduct research. This means locating and studying published material (sources) that are relevant to the topic you are studying. In composing your own written work, you must reference each of these sources. This simply means that you are making it clear to the reader that you have drawn ideas (or quotes, statistics, diagrams, etc.) from another source, and you are clearly identifying that source. Failure to reference your sources correctly is considered plagiarism, as described on the following 4 slides.

3 i) Definition of PLAGIARISM
Plagiarism is the act of copying, including or directly quoting from, the work of another without adequate acknowledgement. The submission of plagiarised materials for assessment purposes or for publication or for public presentation is fraudulent and all suspected cases will be investigated and dealt with appropriately by the University following the procedures outlined here and with reference to the Disciplinary Code. All work submitted by students for assessment purposes is accepted on the understanding that it is their own work and written in their own words except where explicitly referenced using the accepted norms and formats of the appropriate academic discipline. Source: National University of Ireland, Galway. (2007). Code of practice for dealing with plagiarism. Retrieved July 4, 2007, from NUIG, University Code of Conduct, Appendix VI web site: This is the definition of plagiarism as contained in the Code of Conduct of the National University of Ireland, Galway. Further information and clarification can be found at the web site shown above. It is important to note that most cases of plagiarism are inadvertent rather than intentional, i.e. the result of incomplete or incorrect referencing of sources. However, as noted in the Code of practice for dealing with plagiarism (NUI Galway, 2007), it is the responsibility of the student to reference sources correctly: “Whilst some cases of plagiarism can arise through poor academic practice with no deliberate intent to cheat, this still constitutes a breach of acceptable practice and requires to be appropriately investigated and acted upon.” Please see the MScSIS Student Handbook, section 5.1 for further information on plagiarism and the MScSIS Plagiarism Procedure.

4 ii) Why acknowledge sources?
Acknowledge your dependence on another person’s ideas or words Receive credit for your research Establish the credibility & authority of your knowledge and ideas To place your own ideas in context To permit your reader to pursue your topic further To permit your reader to access your sources There are also many positive reasons to acknowledge your sources – it is good academic practice. Once you learn to reference sources correctly, it will be a skill that you will have for the rest of your life. Source: Princeton University. (2007). Acknowledging your sources. Retrieved July 4, 2007, from Academic Integrity at Princeton web site:

5 iii) How to cite sources?
There are 2 parts to citing your sources In-text citations Reference List “direct quotation” (Smith, 2001, p. 45) always on its own page idea according to Smith (2001),… at the end of the thesis Remember – it’s not enough just to list all your sources at the end of an essay! That’s only one-half of correct referencing; you also need to put in-text citations wherever you are referencing the source.

6 iv) Always cite your sources!
1. Select appropriate sources 2. Identify type of source (e.g. book, web page) 3. Determine fields required for that source As noted, a good citation allows the reader to locate the sources you used, either to clarify further or conduct further research. See the APA Publication Manual for further detail on the fields necessary for in-text citations (pp ) and the reference list (pp ). Source: APA (2003). Publication Manual of the American Psychological Association (5th Ed.). Washington, DC: APA. This concludes the short introduction to the Plagiarism and Referencing Sources. The remaining slides in this Lecture continue with Computer Architecture. A good citation allows the reader to locate the source(s) CITATIONS

7 Connecting Components
All the units must be connected, whereby different types of connection are required for different types of unit: Memory Input/Output (I/O) CPU We now move back on to Computer Architecture, namely: the concept of a computer bus and how external devices are connected to a computer and can be accessed by the processor. Connectivity is one of the central issues of computer design. The problem here is that various different subsystems like memory and CPU, each with specific characteristics and requirements, need to be interconnected with each other. Stallings discusses this in detail in sections 3.3 and 3.4. The memory connection deals with memory-specific issues: the connection must be able to transport data between memory and other components. In order to store or access data in well-defined locations within the memory, addresses must be passed on as well. In order to distinguish between read and write accesses to memory, special control signals must be incorporated. The I/O connection has quite similar requirements: data is sent between the computer and peripherals using address information and dedicated control lines. In order to inform each other about events, the computer and peripherals exchange interrupt signals. The CPU is the control centre of the computer system and must be able to send data and control signals to all devices. In addition, it must also receive data and interrupts from system devices.

8 Buses What is a bus? Types of bus
Communication pathway connecting two or more devices Usually broadcast (a number of channels in one bus) Power lines may not be shown Types of bus Data Bus Carries data/instructions Width is a key determinant of performance A bus can be seen as a communication pathway connecting two or more devices. It is usually a broadcast system, whereby every single device “listens” to whatever action is taking place on the bus. In this respect, the inside of the computer is similar to a computer local area network (LAN). On most LANs, all computers can sense the traffic on it, but only “grab” the data when it is addressed to it. A bus might also contain power lines, but they are usually not described or explicitly mentioned. The data bus carries data and instructions. It is typically as wide as the internal CPU registers (for example the accumulator). Therefore a bus has a width of 8-bit, 16-bit, 32-bit or 64-bit.

9 Buses Types of bus Address Bus Control Bus
Identifies the source or destination of data Bus width determines maximum system memory capacity Control Bus Control and timing information, e.g. memory read/write signal, Interrupt request or clock signals The address bus carries information about the location in memory where a data word or an instruction is read from/written to. Since addresses (like data, control lines, etc) are represented as binary signals, a single address line allows a processor to distinguish between 2 addresses (“0” and “1”) and two address lines allow the processor to distinguish between 4 addresses in memory (“00”, “01”, “10” and “11”), etc. A CPU with 16 address lines (like the Intel 8080) can address 2^16 or 64k cells in memory. So, the width of the address bus determines the memory capacity of a computer system. The control bus carries control information (e.g. “read to” or “write from” memory), timing information (e.g. “signal when data is ready to be read from memory”), clock signals (to indicate CPU speed to other components) and interrupt lines. The various control lines, address lines and data lines together form a bus. A typical bus might consist of 16 data lines (to access 16-bit wide data at a time), 16 address lines (to access 64k memory locations) and 10 control lines (for memory read/write, interrupts, etc). Sometimes address and data lines are multiplexed, e.g. shared, and thus reduce the complexity of a bus.

10 What does a Bus look like?
You can easily identify a bus in a computer: A ribbon cable (within each coloured strip is a separate wire) between a hard disk and a circuit board (above left) Parallel lines on a circuit board (above right, between the 2 DD2 numbered chips) Strip connectors on mother boards (like PCI) Sets of wires.

11 Single Bus Problem Lots of devices on one bus leads to propagation delay: Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity Most systems use multiple buses to overcome these problems Implementing a single bus within a computer can cause some serious problems. Since it has to interconnect all the devices, the bus is relatively long. As an electrical signal traverses the bus it needs some time to reach all devices. These delays seem short for a human, but since computers work with very high clock rates, they become increasingly significant. As a result, most systems use multiple buses to overcome this problem.

12 Traditional (ISA) Bus (with cache)
This slide shows the ISA bus, which was a popular PC bus-architecture until recently. The Local Bus connects the processor to the cache and the local I/O controller. The cache, main memory and expansion bus interface are interconnected by the System Bus. The Expansion Bus connects peripherals with the system bus via the expansions bus interface. Can you spot the hierarchy? The most often used and more important components are neared to the CPU and on faster buses. However, all I/O devices are lumped together on the slow expansion bus, regardless of their operating speed or how much data they needed to exchange with the CPU. This layout became inefficient as very fast, high bandwidth I/O devices (e.g. high speed network cards) became common.

13 High Performance Bus In contrast, a High Performance Bus provides different interconnections for components with high bandwidth requirements and therefore increases the overall system performance: Again the Local Bus interconnects the processor with the cache, which in turn is connected with the main memory using the system bus. An additional bridge connects the local bus with the High-Speed Bus, which provides connectivity for high bandwidth/performance components like the graphic card or the SCSI interface. The Expansion Bus looks after low speed components like serial interfaces. It is connected with the high-speed bus via the expansion bus interface.

14 Bus Types Dedicated with separate data and address lines
Multiplexed with shared lines A control line distinguishes between address valid and data valid Advantage: Fewer lines Disadvantages: More complex control & reduced performance Bus Arbitration More than one module (e.g. CPU and DMA controller) controlling the bus Only one module may control bus at one time Arbitration may be centralised or distributed Generally a bus can be dedicated, whereby every single signal has its own line. This huge bus can cause layout or routing problems during the design of the PCB for a computer. Alternatively the number of required lines can be reduced by introducing a multiplexing scheme, whereby a line can either transport an address bit, a data bit or a control bit. Example: A dedicated bus consists of - 16 address lines - 16 data lines - one r/w line (to distinguish between read and write operations to memory) ===== 33 lines in total The same multiplexed bus consists of - 16 lines used for addresses or data - one r/w line (to distinguish between read and write operations to memory) - one a/d line (to distinguish between address and data being transported by the 16-bit bus) 18 lines in total Bus arbitration is required, if more than one module attached to the bus can control the bus.

15 Bus Arbitration Centralised Arbitration Distributed Arbitration
Single hardware device (the bus controller or arbiter) controlling bus access May be part of CPU or separate Distributed Arbitration Each module may claim the bus Control logic on all modules In centralised arbitration a single hardware device decides which module can use the bus. In distributed arbitration each module can claim the bus and a control logic (placed on all modules) decides which module will be in control of the bus.

16 PCI Bus 32 or 64 bit Peripheral Component Interconnection
Usually runs in 32 bit mode at 33Mhz = 133MBps 64 bit mode at 66MHz = 528MBps Intel released to public domain 49 mandatory lines & 51 optional lines PCI Commands Transaction between initiator (master) and target Master claims bus Determine type of transaction (read or write) Address phase One or more data phases The PCI bus is a high-speed bus for peripheral component interconnection and replaced the ISA bus in PC architectures in recent years. Stallings describes it in detail in section 3.5. Required PCI Lines System lines including clock and reset 32 multiplexed address and data lines Interface control including error lines Arbitration (not shared) Optional PCI Lines Interrupt lines Cache support 64 bit bus extension JTAG/boundary scan for testing procedures

17 PCI Bus The PCI bus is connected to the processor via a bridge (also called north-bridge). The expansion bus bridge (or south-bridge) connects the PCI bus with the expansion bus.

18 PCI Bus Here is an example of a PCI card that you can plug into your PC’s motherboard. All PCs have what are known as expansion slots to allow easy upgrading of the computer system. These expansion slots allow you to easily add a new device to your system. However, you have to know what kind of slots (i.e. buses) you have in your PC. Otherwise, you could buy a new device and find you can’t plug it in to your motherboard. Almost all PCs nowadays have PCI slots on their motherboard. These are the 5 parallel white slots shown above on the right. The device on the top left is a video card, which you might buy to improve your gaming performance. Notice the PCI connector on the bottom which fits snugly into the white slots in the other picture. Other common expansion slot types are ISA, AGP (fast, specialised for graphics) and PCI Express (the newer, faster version of PCI). It is common to find motherboards with a number of different expansion slots on it for maximum upgrade flexibility. The expansion slots for the various bus types all use different connectors and thus are different sizes. This is to prevent you plugging a device into the wrong bus. The picture on the bottom left above shows A PCI slot and the longer ISA slot underneath it. Thus ,with a bit of experience you can tell what bus type a device is by looking at the connector on the bottom. We’ll have a little test of this on slide 15.

19 Input/Output (I/O) I/O Devices Input/Output Problems
External Memory - Hard & Floppy Disks, CD-ROM Human Readable - Screen, printer, keyboard Machine Readable- Monitoring and control Communications - Modem, Network Interface Card Input/Output Problems Wide variety of peripherals, which deliver different amounts of data at different speeds and in different formats (word or block), e.g. Keyboard or mouse < 1 Kilobits per second (kbps) Fast Ethernet 100 Megabits per second (Mbps) All slower than CPU and RAM A computer consists of various I/O devices or peripherals. These deliver data of different amounts and at different speeds using various formats. In order to access these peripherals (either for read or for write operations), I/O modules are used. I/O modules are an abstraction of peripherals. Refer to Stallings (7.1) for more information. An example of an I/O device is the Intel 82C55A chip, which provides 24 input/output lines (organised in 3 blocks of 8 bits each). This module was used in Personal Computers in the 80s and 90s to provide a parallel interface. This interface was used to connect printers and scanners with a PC. Today, it is widely replaced by the USB interface.

20 I/O Devices Above are pictures of what I/O devices that are we are familiar with and probably take for granted. The only 2 items not particularly obvious are those on the right. On top, there is a modem card and underneath it is a CD-ROM drive. Q. What type of bus does the modem card plug into? (hint: refer to slide 13) A. On next slide…..

21 Typical I/O Device Data Rates
A. It is an ISA modem. Note the long connector on the bottom of the card – a dead give away! Did you notice that the card would fit in the ISA slot on slide 13? The diagram above shows the typical I/O rates that can be achieved by various I/O devices: A keyboard has a data rate of up to 100 bps (equivalent to approximately 12 keyboard hits per second), while a graphics display has a data rate of approximately 600 Mbps.

22 I/O Modules Abstract and simplify the interaction between the CPU the peripheral Provide internal interfaces (CPU/Mem  I/O module) and external interfaces (I/O module  actual device) I/O Module Functions Control and timing as well as error detection CPU communication Data buffering - CPU/Main Memory - high data rate - I/O devices - vary from very low to high - I/O module uses buffers to match data rates between CPU and I/O device I/O modules (Stallings, section 7.2) abstract and simplify the interaction between the CPU and the peripheral by providing internal and external interfaces. The Intel 80C55A, for example, provided a parallel interface which can be used to connect a wide range of external devices. The same set of registers, control lines, etc. is used regardless of the connected device.

23 Generic I/O Scenario: Peripheral to CPU Transfer
CPU checks I/O module device status I/O module returns status If ready, CPU requests data transfer I/O module gets data from device I/O module transfers data to CPU Remark: internal (CPU) & external (device) communication is required This slide shows the general concept of an I/O scenario. It describes the interaction between the CPU, the I/O module and the device. The first, second, third and fifth steps in the example above use the internal interface, while the fourth step requires the external interface.

24 I/O Module Diagram This diagram shows the components of an I/O module. Address, data and control lines of the internal interface allow the CPU to access data registers and status/control registers, whereby every register has a unique address. Every single I/O module provides a similar API to the internal interface. The external interface is provided through the external device interface logic, which generates control signals used by peripherals as well as handling status information, and the data being transmitted.

25 Input/Output Techniques
Programmed Interrupt driven Direct Memory Access (DMA) Programmed I/O CPU has direct control over I/O Sensing status Read/write commands Transferring data CPU waits for I/O module to complete operation Programmed I/O wastes CPU time There are three I/O techniques which allow data exchange between the processor and the peripheral. They differ in the amount of CPU interventions that are required to perform an I/O task. Programmed I/O (Stallings, section 7.3) is the simplest of the three methods, whereby the CPU has the highest workload and is least efficiently used: Apart from issuing read or write commands, it also has to transfer data to or from the I/O module. The CPU also monitors the status of the I/O module in order to determine if it has completed its operation or not.

26 Programmed I/O: Detail
CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically I/O module does not inform CPU directly I/O module does not interrupt CPU Let us assume that a scanner is connected to a PC using a parallel interface. Within the PC the CPU is connected with the parallel interface via a 82C55A module. The task is to read a number of bytes (representing a digitized section of a document) from the scanner. The CPU issues a read command to the 82C55A, which in turn pulls a single byte from the scanner device and stores it in an internal register. This process might take some time and therefore the I/O module will set an internal flag to indicate that the read operation is over. The CPU on the other hand polls this flag continuously. Once the processor detects that the flag is set, it will reset the flag, read the byte stored in the register and store it in memory. This process is repeated, until all bytes are captured. If the 82C55A gets stuck, e.g. if the scanner fails during the scanning process and the read process cannot be finished, the CPU could issue a timeout (because the ready-flag is not set) and raise an alarm or deal with the error condition.

27 Interrupt Driven I/O Overcomes CPU waiting
No repeated CPU checking of device I/O command issued CPU undertakes other work CPU checks for interrupt at end of each instruction cycle I/O module interrupts when ready CPU saves context etc. Processes interrupt Reloads context and continues Interrupt driven I/O (Stallings, section 7.4) in contrast works slightly differently and avoids the active polling of the ready-flag in the example on the previous slide. Once the device sets the flag, it also raises a CPU interrupt. This implies that there is a physical connection between a 82C55A “data ready” output pin and the CPU interrupt input pin. Once the interrupt is raised the CPU saves the context (e.g. the register contents of the program currently being executed) and executes an interrupt handler, which reads the byte from the module and stores it in memory. Once this operation is finished, the interrupt handler terminates and the context of the original program is reloaded.

28 Interrupt Processing This slide shows the concept of interrupt driven I/O as a flowchart. It distinguishes between action taken by hardware (CPU/device) and by software (interrupt service routine). In addition to the explanations on the previous slide the processor also signals the acknowledgement of the interrupt to the I/O module. This handshake mechanism allows the I/O module to keep track of accepted/processed interrupts.

29 Interrupt Driven I/O: Basic Operation
CPU issues read command I/O module gets data from peripheral whilst CPU does other work I/O module interrupts CPU CPU requests data I/O module transfers data This flowchart shows interrupt driven I/O. It is quite similar to the flowchart describing programmed I/O, but incorporates the changes associated with the interrupt mechanism in the upper half of the diagram.

30 Identifying the Interrupting Module
Different line for each module Limits number of devices Software poll CPU asks each module in turn – slow! Daisy chain or hardware poll Interrupt Acknowledge sent down a chain Module responsible places vector on bus CPU uses vector to identify handler routine Bus master Module must claim the bus before it can raise interrupt e.g. PCI & SCSI Interrupt driven I/O is a very efficient method of exchanging data between an external device, an I/O module and the CPU. But it also raises the question of how a CPU can distinguish between various I/O modules, each of them associated with a specific interrupt handler. One very common way to deal with this problem is to use an individual interrupt line for each module. Since every interrupt line is associated with its individual interrupt service routine (tailored for the module it is associated with), the CPU can deal with different module types. The obvious disadvantage of this approach is that a processor has only a limited number of interrupt inputs (e.g. 3 – 8). Alternatively all modules can share the same interrupt line. In this case the CPU has to check every single I/O module connected to the line in order to determine which one has raised the interrupt. In order to do this the CPU can read internal registers in each I/O module, since all modules are accessible to the CPU via the system bus. The interrupt handler consist of a number of routines (one for each module) and, depending on the outcome of the module polling, the processor branches to the right one and executes it. A significant disadvantage of this approach is the relatively large amount of time it takes to poll all I/O modules. In a daisy chain or hardware poll all devices share a single interrupt line. The CPU acknowledges each interrupt request by sending a signal to the modules using a dedicated line. The modules are daisy-chained along this line (i.e. the output of the first module is connected to the input of the second module, etc). Once a module receives the acknowledge, it will pass it on to the next module, if it did not raise the interrupt. The module which raised the interrupt will place a vector (i.e. a unique identifier) on the bus, which will be read by the CPU and allows it to identify the module. In a bus master scenario the module must claim the bus before it can raise an interrupt. This allows the module to be identified.

31 Multiple Interrupts An interrupt handler can be interrupted because of a new interrupt request with higher priority Different line for each module Each interrupt line has a priority Software poll Poll higher priority devices first Daisy chain or hardware poll Higher priority devices first in daisy chain Bus master If bus mastering only current master can interrupt If multiple modules are using interrupt-driven I/O, interrupt requests with different priorities can be raised simultaneously. If each module has its own interrupt line (each with its (programmed) priority), the CPU makes the decision on-the-fly which interrupt it has to deal with first or if an interrupt handler for one module will be interrupted to give priority to another handler. If a shared interrupt line is used, the CPU cannot interrupt one interrupt handler for the sake of another with higher priority. All it can do is choose the module with the highest priority among a set of simultaneous interrupt requests by polling higher priority devices first. If modules form a daisy chain, the processor has the same capabilities as when each module has its own line. In a bus mastering scenario the interrupt-requesting module with the highest priority becomes the master. Once this decision is made, no other module (if it has higher priority) can become master, until the bus is released again.

32 Direct Memory Access (DMA)
Interrupt driven and programmed I/O require active CPU intervention Transfer data is limited, the CPU is tied up DMA is the answer: a DMA controller is another module (hardware) on the bus Takes over from CPU for I/O DMA Operation CPU tells DMA controller details about operation CPU carries on with other work DMA controller deals with transfer DMA controller sends interrupt when finished Both programmed I/O and interrupt-driven I/O require the CPU to transfer data between the I/O module and its internal registers and from there to internal memory. The achievable data transfer rate is limited and valuable processor time, which could be used by a more sophisticated task, is wasted. The solution to this dilemma is Direct Memory Access (DMA), described in Stallings, section 7.5. A special hardware component, the DMA controller, allows the transport of data within and between internal memory and/or I/O devices. The CPU has to do very little to support this: It has to program the DMA controller with the details of the data transfer (e.g. source address, destination address, number of bytes or words to be transferred, etc.). Once the data transfer is finished, the CPU is informed by the DMA controller via an interrupt.

33 DMA Transfer Cycle Stealing
DMA controller takes over bus for a cycle Transfer of one word of data CPU suspended just before it accesses bus (reads/writes from/to memory) Slows down CPU but not as much as CPU doing transfer The DMA controller must take control of the bus in order to transfer data from a source to a destination. The CPU, on the other hand, works on other tasks concurrently. Since it has to access memory to read the instructions from memory (and therefore has to take control of the bus) as well, a bus access conflict may happen. This problem is avoided by applying the following strategy (see also the image above): The DMA controller transfers only one word of data at a time. There are specific breakpoints during an instruction cycle, where the DMA controller is allowed to access the bus and suspends the CPU. Interrupts (particularly from the DMA controller) are only accepted by the processor during an interrupt breakpoint. Although the CPU is slowed down by this process, the combined performance of the DMA controller and the CPU is still better than if the CPU was working on its own.

34 DMA Configurations Single bus, detached DMA controller
Each transfer uses bus twice, CPU is suspended twice Single bus, integrated DMA controller Each transfer uses bus once, CPU is suspended once The DMA transfer of a single word consists of the following steps: Move data from source to DMA controller. Move data from DMA controller to destination. This means that in a detached DMA controller configuration (see picture on slide) every transfer must access the bus twice, while the CPU is suspended twice. The number of bus accesses can be reduced to one per word transfer, if every single I/O device is connected directly to a DMA controller. The DMA controller itself is connected to the system bus in order to access the destination (in this case the internal memory). This configuration is called integrated DMA. Note: The integrated DMA controller configuration as shown above optimises the data transport between an I/O device and internal memory. It does not allow data transport between I/O devices.

35 DMA Configurations Separate I/O bus
Bus supports all DMA enabled devices Each transfer uses bus once, CPU is suspended once The separate I/O bus is another possible configuration, where all devices are connected to a single DMA controller via an I/O bus. Again the number of accesses to the system bus is reduced to one per word transfer and the CPU is suspended once.

36 Techniques for Data Input
The slide shows the flowcharts for the three I/O methods side by side: programmed I/O Interrupt driven I/O DMA as discussed on the previous slides. Which looks the most efficient?!

37 I/O Channels I/O devices getting more sophisticated
Have their own processor/memory (e.g. 3D graphics cards) CPU instructs I/O controller to do transfer I/O controller does entire transfer Improves speed: takes load off CPU I/O channels (Stallings, section 7.6) are another improvement over DMA. They contain their own hardware like processors and memory and allow a quicker and more sophisticated data transfer within the computer than the previous solutions. I/O controllers are still managed by the CPU, since the latter has to provide details about the data transfer task, similar to a DMA transfer.

38 In This Lecture, You Have Learned …
Computer buses Data bus versus address bus versus control bus Traditional buses versus high-performance buses Bus types and bus arbitration Synchronous versus asynchronous timing The PCI and the AGP bus I/O devices Typical I/O scenarios and expected data rates I/O modules and I/O module functions I/O scenarios I/O techniques: programmed I/O, interrupt driven I/O, DMA Handling multiple I/O tasks using interrupt driven I/O This concludes Workshop 2, part 1 In part 2 we will discuss external interfaces as well as the different types of internal memory found in a computer.

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