1. Decay Spectroscopy at FAIR Using the Advanced Implantation Detector Array (AIDA) presented by Tom Davinson on behalf of the AIDA collaboration Tom Davinson School of Physics The University of Edinburgh

2. Presentation Outline What? Where? Why? How? Who?

3. Cost –Approx €1000M –€650M central German government –€100M German regional funding –€250M from international partners Timescale –Feb 2006- German funds in budget 2007-14 –2007 start construction –2012 phased start experiments –2014 completion NUSTAR Super FRS Future facility 100 m GSI today SIS 100/300 UNILAC ESR SIS 18 HESR RESR NESR FAIR: Facility for Antiproton and Ion Research

4. NUSTAR: Nuclear Structure Astrophysics & Reactions Exotic (radioactive) beams formed by fragmentation, selected by separator. HiSpec :gamma spec DeSpec :decay spec LASPEC: laser spec MATS: Penning traps Stored beam (rings): EXL : hadron scattering ELISe : electron scattering AIC : antiproton scattering R 3 B: reactions

5. FAIR: Production Rates from FAIR CDR, section 2 Predicted Lifetimes > 100ns

6. r-process Nucleosynthesis along neutron-rich side of valley of stability via s-process and r-process s-process – Red Giants, long timescales, moderate n-flux nucleosynthesis close to valley r-process – Supernova type II?, timescales ~seconds?, high n-flux? nucleosynthesis far from valley equilibrium (n,  ) and ( ,n) reactions? n-capture until binding energy becomes small wait for  decay to nuclei with higher binding energy effect of neutron magic numbers – 82, 126? Require: nuclear masses (r-process pathway)  decay half lives (abundance along pathway)  -delayed neutron emission probabilities (abundance modification)

7. NUSTAR: DESPEC/HISPEC

8. DESPEC: Implantation DSSD Concept Super FRS Low Energy Branch (LEB) Exotic nuclei – energies ~50-150MeV/u Implanted into multi-plane, highly segmented DSSD array Implant - decay correlations Multi-GeV DSSD implantation events Observe subsequent p, 2p, , , ,  p,  n … decays Measure half lives, branching ratios, decay energies …

9. Implantation DSSD Configurations Two configurations proposed: a)8cm x 24cm “cocktail” mode many isotopes measured simultaneously b) 8cm x 8cm high efficiency mode concentrate on particular isotope(s)

10. DSSD Segmentation We need to implant at high rates and to observe implant – decay correlations for decays with long half lives. DSSD segmentation ensures average time between implants for given x,y quasi-pixel >> decay half life to be observed. Implantation profile  x ~  y ~ 2cm  z ~ 1mm Implantation rate (8cm x 24cm) ~ 10kHz, ~kHz per isotope (say) Longest half life to be observed ~ seconds Implies quasi-pixel dimensions ~ 0.5mm x 0.5mm Segmentation also has instrumentation performance benefits

11. DSSD Technology well established (e.g. GLAST LAT tracker) 6” wafer technology 10cm x 10cm area 1mm wafer thickness Integrated components a.c. coupling polysilicon bias resistors … important for ASICs Series strip bonding 8.95 cm square Hamamatsu-Photonics SSD before cutting from the 6-inch wafer. The thickness is 400 microns, and the strip pitch is 228 microns.

12. Kapton readout cables. Tested SSDs procured from Hamamatsu Photonics 19 “trays” stack to form one of 16 Tracker modules. Electronics and SSDs assembled on composite panels. 4 SSDs bonded in series. Composite panels, with tungsten foils bonded to the bottom face. 2592 10,368 342 648 342 18 Carbon composite side panels Chip-on-board readout electronics modules. Electronics mount on the tray edges. “Tray” GLAST: Large Area Telescope (LAT) Silicon Tracker from R.P.Johnson et al.

13. ASIC Compatible Silicon Strip Detectors But … Design complexity more photomasks higher NRE costs (c. £40k) Production complexity more processing steps lower overall yields higher production costs (c. £5k per wafer) Larger area (6” wafers) more restricted range of wafer thicknesses Fractional active area low DSSSD strips 625  m pitch, 575  m width => fractional active area 85%

14. AIDA: DSSD Array Design 8cm x 8cm DSSDs common wafer design for 8cm x 24cm and 8cm x 8cm configurations 8cm x 24cm 3 adjacent wafers – horizontal strips series bonded 128 p+n junction strips, 128 n+n ohmic strips per wafer strip pitch 625  m wafer thickness 1mm  E, Veto and 6 intermediate planes 4096 channels (8cm x 24cm) overall package sizes (silicon, PCB, connectors, enclosure … ) ~ 10cm x 26cm x 4cm or ~ 10cm x 10cm x 4cm Implantation depth? Stopping power? Ge  detector? Calibration? Radiation damage? Cooling? courtesy B.Rubio

15. AIDA: Instrumentation Requirements Large number of channels required, limited available space and cost mandate use of Application Specific Integrated Circuit (ASIC) technology. Requirements Selectable gain:low 20GeV FSR : intermediate ? : high 20MeV FSR Noise  ~ 5keV rms. Selectable threshold: minimum ~ 25keV @ high gain ( assume 5  ) Integral and differential non-linearity Autonomous overload recovery ~  s Signal processing time <10  s (decay-decay correlations) Receive timestamp data Timing trigger for coincidences with other detector systems DSSD segmentation reduces input loading of preamplifier and enables excellent noise performance.

16. AIDA: Instrumentation Requirements contd. Preamplifier overload recovery per D.A.Landis et al., IEEE NS 45 (1998) 805 Originally developed for spaceborne HPGe detectors – possible application for back detectors of DESPEC  -ray detector array?

17. AIDA: ASIC Concept courtesy I.Lazarus, CCLRC DL - Example design concept - 1 channel of 16 channel ASIC (shown with external FPGA and ADC) - FEE-integrated DAQ - Digital data via fibre-optic cable to PC-based data concentrator/event builder

18. ASICs: Reality Check The Bad News (and there’s quite a bit)… CMOS design environment passives temperature & voltage dependent area constrains component values parasitic effects poor control of absolute component values Modelling empirical data required time consuming Entry costs MPW – shared NRE costs, higher production costs dedicated – high NRE costs, lower production costs Risk CMOS production process lifetime Limited dynamic range ~2,000:1 (cf. RAL108 ~100,000:1) ASIC channel pitch constrains detector strip pitch The reality is that there are significant design and engineering limitations … compromise will be necessary.

19. ASICs: Reality Check However, there is some Good News … Mature technology Capability derived from particle, space & X-ray applications Radiation hardness. Sadrozinski, IEEE NS48 (2001) 933 cf. G.E.Moore, Electronics, 19 April 1965 Yokoyama et al., IEEE NS48 (2001) 440

20. AIDA: General Arrangement

21. ASICADC Virtex 4FX FPGA Power Supplies and other components Fibre Driver (Laser) for Ethernet 16 ch ASIC (with ADC?) Estimated size: 80x220mm, Estimated power 25W per 128ch (800W total) 128 detector signals in; 1 data fibre out Ethernet MAC ASICADCASICADCASICADCASICADCASICADCASICADCASICADC AIDA: 128 channel FEE Card Concept courtesy I.Lazarus, CCLRC DL

22. Front End Electronics Data output stage standard format and output medium e.g. 10G Ethernet fibre Correlate by timestamp Clock and Timestamp BUTIS Common Clocks 10/200MHz <100ps/km Slow Control Common database loaded into local controllers over Ethernet Detector HV etc. NUSTAR: Common DAQ Interfaces courtesy I.Lazarus, CCLRC DL

23. Slow Control BUTIS Timestamps Data Output Switch PC Farm AIDA: System Concept courtesy I.Lazarus, CCLRC DL

24. AIDA: Current Status Edinburgh – Liverpool – CCLRC DL – CCLRC RAL collaboration - 4 year grant period - DSSD design, prototype and production - ASIC design, prototype and production - Integrated Front End FEE PCB development and production - Systems integration - Software development Deliverable: fully operational DSSD array to DESPEC Proposal approved EPSRC Physics Prioritisation panel meeting April 2006 EPSRC award announcement letters received June 2006 Detailed specification development has commenced M0 – specification finalised and critical review

25. Resources Cost Total value of fEC proposal c. £2.3M (incl. PG c. £2.6M) Support Manpower CCLRC DLc. 4.2 SYFEE PCB Design DAQ h/w & s/w CCLRC RALc. 3.5 SYASIC Design & simulation ASIC Production Edinburgh/Liverpoolc. 4.5 SYDSSD Design & production FEE PCB production Mechanical housing/support Platform grant support CCLRC DL/Edinburgh/Liverpool

26. AIDA: Workplan

27. AIDA: Project Partners The University of Edinburgh (lead RO) Phil Woods et al. The University of Liverpool Rob Page et al. CCLRC DL & RAL John Simpson et al. Project Manager: Tom Davinson Further information: http://www.ph.ed.ac.uk/~td/AIDA

28. Acknowledgements Presentation includes material from other people. Thanks to: Ian Lazarus (CCLRC DL) Haik Simon (GSI) Berta Rubio (IFIC, CSIC University of Valencia)

31. Problem Multi GeV implant followed by decay in region of 1MeV e.g. 20GeV/1MeV = 2.10 4 dynamic range Some possible solutions Logarithmic preamps Makes analysis difficult High/low gain preamp pairs (with clamping) Doubles power, halves packing density Fast recovery from saturation Look at this one first ASIC Design Challenge

32. NUSTAR: Low Energy Branch

33. AIDA: Project Summary Objective: To construct a new generation ASIC-based Double-sided Silicon Strip Detector system for decay spectroscopy experiments of exotic nuclei on the new FAIR accelerator facility at GSI, Darmstadt, Germany. To commission and test this system in-beam, and perform ongoing implantation-decay experiments, primarily at GSI, prior to the availability of beams from FAIR. 4 years funding from 2006-2010 announced May 2006 Collaboration: Detectors and project management- University of Edinburgh FEE, ASIC, DAQ - CCLRC Postdoc (detector/physics) Mechanics- University of Liverpool Total 35 – 40 FTE allocated to this project (scientists, engineers, mechanical designers, technicians)