Presentation is loading. Please wait.

Presentation is loading. Please wait.

VLSI Testing 304-649 Jean-François Boland Design error and fault simulation.

Similar presentations


Presentation on theme: "VLSI Testing 304-649 Jean-François Boland Design error and fault simulation."— Presentation transcript:

1 VLSI Testing Jean-François Boland Design error and fault simulation

2 Presentation Plan Project Overview Design error and fault models ESIM Software Future work

3 Project Overview Simulation – Design error – Logical fault ESIM software, [Al-Asaad 00], [Hayes 00] – Fault and design errors models – Algorithms use for faults/errors simulation – Experimental results and performances

4 Error models Gate Substitution Errors (SIGSE, MIGSE) – 67% of all manual design errors Gate Count Errors (EGE, MGE) Input Count Errors (EIE, MIE) Wrong Input Errors (WIEs) Single Stuck-Line (SSL) Input Pattern (IP) Design error Fault error

5 Examples of design errors

6 ESIM Software Written using C++ (open source) Simulation algorithms for GP1 and GP2 errors Uses the netlist format of the ISCAS-85 benchmark circuits. Specifications Application Evaluate the coverage of design errors and logical faults of typical ATPG.

7 Future work GP1 and GP2 algorithms overview. Performances and experimental results analysis. ESIM functionality requirements. Limits and improvements.


Download ppt "VLSI Testing 304-649 Jean-François Boland Design error and fault simulation."

Similar presentations


Ads by Google