Presentation is loading. Please wait.

Presentation is loading. Please wait.

The IA-64 Architectural Innovations Hardware Support for Software Pipelining José Nelson Amaral 1.

Similar presentations


Presentation on theme: "The IA-64 Architectural Innovations Hardware Support for Software Pipelining José Nelson Amaral 1."— Presentation transcript:

1 The IA-64 Architectural Innovations Hardware Support for Software Pipelining José Nelson Amaral 1

2 Suggested Reading 2 Intel IA-64 Architecture Software Developer’s Manual, Chapters 8, 9

3 Instruction Group 3 An instruction group is a set of instructions that have no read after write (RAW) or write after write (WAW) register dependencies. Consecutive instruction groups are separated by stops (represented by a double semi-column in the assembly code). ld8r1=[r5]// First group subr6=r8, r9// First group addr3=r1,r4 ;;// First group st8[r6]=r12// Second group

4 Instruction Bundles 4 Instructions are organized in bundles of three instructions, with the following format: instruction slot 2instruction slot 1instruction slot 0template

5 Bundles 5 In assembly, each 128-bit bundle is enclosed in curly braces and contains a template specification {.mii ld4r28=[r8] // Load a 4-byte value addr9=2,r1 // 2+r1 and put in r9 addr30=1,r1 // 1+r1 and put in r30 } An instruction group can extend over an arbitrary number of bundles.

6 Templates 6 There are restrictions on the type of instructions that can be bundled together. The IA-64 has five slot types (M, I, F, B, and L), six instruction types (M, I, A, F, B, L), and twelve basic template types (MII, MI_I, MLX, MMI, M_MI, MFI, MMF, MIB, MBB, BBB, MMB, and MFB). The underscore in the bundle accronym indicates a stop. Every basic bundle type has two versions: one with a stop at the end of the bundle and one without.

7 Control Dependency Preventing Code Motion 7 addr7=r6,1// cycle 0 addr13=r25, r27 cmp.eq p1, p2=r12, r23 (p1) br. condsome_label ;; ld4r2=[r3] ;;// cycle 1 sub r4=r2, r11// cycle 3 ld br block A block B In the code below, the ld4 is control dependent on the branch, and thus cannot be safely moved up in conventional processor architectures.

8 Control Speculation 8 (p1) br.cond.dptk L1// cycle 0 ld8 r3=[r5] ;;// cycle 1 shr r7=r3,r87// cycle 3 In the following code, suppose a load latency of two cycles However, if we execute the load before we know that we actually have to do it (control speculation), we get: ld8.s r3=[r5]// earlier cycle // other, unrelated instructions (p1) br.cond.dptk L1;;// cycle 0 chk.s r3, recovery// cycle 1 shr r7=r3,r87// cycle 1

9 Control Speculation 9 ld8.s r3=[r5]// earlier cycle // other, unrelated instructions (p1) br.cond.dptk L1;;// cycle 0 chk.s r3, recovery// cycle 1 shr r7=r3,r87// cycle 1 The ld8.s instruction is a speculative load, and the chk.s instruction is a check instruction that verifies if the value loaded is still good.

10 Ambiguous Memory Dependencies 10 An ambiguous memory dependency is a dependence between a load and a store, or between two stores, where it cannot be determined if the instructions involved access overlapping memory locations. Two or more memory references are independent if it is known that they access non-overlapping memory locations.

11 Data Speculation 11 An advanced load allows a load to be moved above a store even if it is not known wether the load and the store may reference overlapping memory locations. st8[r55]=r45// cycle 0 ld8r3=[r5] ;;// cycle 0 shrr7=r3,r87// cycle 2 ld8.ar3=[r5] ;;// Advanced Load // other, unrelated instructions st8[r55]=r45// cycle 0 ld8.cr3=[r5] ;;// cycle 0 - check shrr7=r3,r87// cycle 0

12 Moving Up Loads + Uses: Recovery Code 12 st8[r4] = r12 // cycle 0: ambiguous store ld8r6 = [r8] ;; // cycle 0: load to advance addr5 = r6,r7 // cycle 2 st8[r18] = r5 // cycle 3 Original Code ld8.ar6 = [r8] ;; // cycle -3 // other, unrelated instructions addr5 = r6,r7 // cycle -1; add that uses r6 // other, unrelated instructions st8[r4]=r12 // cycle 0 chk.ar6, recover // cycle 0: check back: // Return point from jump to recover st8[r18] = r5 // cycle 0 recover: ld8r6 = [r8] ;; // Reload r6 from [r8] addr5 = r6,r7 // Re-execute the add brback // Jump back to main code Speculative Code

13 ld.c, chk.a and the ALAT 13 The execution of an advanced load, ld.a, creates an entry in a hardware structure, the Advanced Load Address Table (ALAT). This table is indexed by the register number. Each entry records the load address, the load type, and the size of the load. When a check is executed, the entry for the register is checked to verify that a valid enter with the type specified is there.

14 ld.c, chk.a and the ALAT 14 An entry e is removed from the ALAT when: (1) A store overlaps with the memory locations specified in e; (2) Another advanced load to the same register is executed; (3) There is a context switch caused by the operating system (or hardware); (4) Capacity limitation of the ALAT implementation requires reuse of the ALAT slot.

15 Not a Thing (NaT) 15 The IA-64 has 128 general purpose registers, each with 64+1 bits, and 128 floating point registers, each with 82 bits. The extra bit in the GPRs is the NaT bit that is used to indicate that the content of the register is not valid. NaT=1 indicates that an instruction that generated an exception wrote to the register. It is a way to defer exceptions caused by speculative loads. Any operation that uses NaT as an operand results in NaT.

16 If-conversion 16 If-conversion uses predicates to transform a conditional code into a single control stream code. if(r4) { add r1= r2, r3 ld8 r6=[r5] } cmp.nep1, p0=r4, 0 ;; Set predicate reg (p1) addr1=r2, r3 (p1) ld8r6=[r5] if(r1) r2 = r3 + r3 else r7 = r6 - r5 cmp.ne p1, p2 = r1, 0 ;; Set predicate reg (p1) addr2 = r3, r4 (p2) subr7 = r6,r5

17 Optimization of Loops 17 Instructions Description: ld4r4 = [r5], 4 ;;r4  MEM[r5] r5  r5 + 4 st4[r6] = r7, 4MEM[r6]  r7 r6  r6 + 4 br.cloopL1if LC  0 then LC  LC -1 goto L1 void f(int *p, int *q, int A, int N){ int t, c; for(c=0 ; c

18 Optimization of Loops 18 (a) L1: ld4 r4 = [r5], 4 ;; (b) add r7 = r4, r9 ;; (c) st4 [r6] = r7, 4 (d) br.cloop L1 ;; a 1 2b 3c/d 4a 5 6 b 7 8a 9 10b Cycles Iterations 11c/d 12a 13 14b If LC=1000, how long does it take for this loop to execute? It takes 4000 cycles.

19 Optimization of Loops: Loop Unrolling 19 (a) L1: ld4 r4 = [r5], 4 ;; (b) ld4 r14 = [r5], 4 ;; (c) add r7 = r4, r9 ;; (d) add r17 = r14, r9 (e) st4 [r6] = r7,4 ;; (f) st4 [r6] = r17,4 (g) br.cloop L1 ;; Cycles Iterations a 1b 2c 3d/e 4f/g 5a 6b 7c 8d/e 9f/g 10a 11b 12c 13d/e 14f/g For simplicity we assume that N is a multiple of 2. Because the loads (a) and (b) both update r5 they have to be serialized

20 Optimization of Loops: Loop Unrolling 20 (a) L1: ld4 r4 = [r5], 4 ;; (b) ld4 r14 = [r5], 4 ;; (c) add r7 = r4, r9 ;; (d) add r17 = r14, r9 (e) st4 [r6] = r7,4 ;; (f) st4 [r6] = r17,4 (g) br.cloop L1 ;; Cycles Iterations a 1b 2c 3d/e 4f/g 5a 6b 7c 8d/e 9f/g 10a 11b 12c 13d/e 14f/g If LC=1000 for the original loop, how long does it take for this loop to execute? It takes 2500 cycles. Thus the loop is 4000/2500 = 1.6 times faster

21 Optimization of Loops: Expanding the Induction Variable 21 add r15 = 4, r5 add r16 = 4, r6 ;; (a) L1: ld4 r4 = [r5], 8 (b) ld4 r14 = [r15], 8 ;; (c) add r7 = r4, r9 (d) add r17 = r14, r9 (e) st4 [r6] = r7,8 ;; (f) st4 [r16] = r17,8 (g) br.cloop L1 ;; Cycles Iterations a/b 1 2c/d 3e/f/g 4a/b 5 6c/d 7e/f/g 8a/b 9 10c/d 11e/f/g 12a/b 13 14c/d We use twice as many functional units as the original code. But no instruction is issued in cycle 1, and functional units are still under-utilized.

22 Optimization of Loops: Expanding the Induction Variable 22 add r15 = 4, r5 add r16 = 4, r6 ;; (a) L1: ld4 r4 = [r5], 8 (b) ld4 r14 = [r15], 8 ;; (c) add r7 = r4, r9 (d) add r17 = r14, r9 (e) st4 [r6] = r7,8 (f) st4 [r6] = r17,8 (g) br.cloop L1 ;; Cycles Iterations a/b 1 2c/d 3e/f/g 4a/b 5 6c/d 7e/f/g 8a/b 9 10c/d 11e/f/g 12a/b 13 14c/d If LC=1000 for the original loop, how long does it take for this loop to execute? It takes 2000 cycles. Thus the loop is 4000/2000 = 2.0 times faster

23 Optimization of Loops: Further Loop Unrolling 23 add r15 = 4, r5 add r25 = 8, r5 add r35 = 12, r5 add r16 = 4, r6 add r26 = 8, r6 add r36 = 12, r6 ;; add r16 = 4, r6 ;; (a) L1: ld4 r4 = [r5], 16 (b) ld4 r14 = [r15], 16 ;; (c) ld4 r24 = [r25], 16 (d) ld4 r34 = [r35], 16 ;; (e) add r7 = r4, r9 (f) add r17 = r14, r9;; (g) st4 [r6] = r7,16 (h) st4 [r16] = r17,16 (i) add r27 = r24, r9 (j) add r37 = r34, r9 ;; (k) st4 [r26] = r27, 16 (l) st4 [r36] = r37, 16 (m) br.cloop L1 ;; Iterations Cycles a/b 1c/d 2e/f 3g/h/i/j 4k/l/m 5a/b 6c/d 7e/f 8g/h/i/j 9k/l/m 10a/b 11c/d 12e/f 13g/h/i/j 14k/l/m

24 Optimization of Loops: Further Loop Unrolling 24 Iterations Cycles a/b 1c/d 2e/f 3g/h/i/j 4k/l/m 5a/b 6c/d 7e/f 8g/h/i/j 9k/l/m 10a/b 11c/d 12e/f 13g/h/i/j 14k/l/m If LC=1000 for the original loop, how long does it take for this loop (unrolled 4 times) to execute? It takes 250*5=1250 cycles. Thus the loop is 4000/1250 = 3.2 times faster

25 Loop Optimization: Loop Unrolling 25 In the previous example we obtained a good utilization of the functional units through loop unrolling. But at the cost of code expansion and higher register pressure. Software Pipelining offers an alternative by overlapping the execution of operations from multiple iterations of the loop.

26 Loop Optimization: Software Pipelining 26 (S1) ld4 r4 = [r5], 4 (S2) (S3) add r7 = r4, r9 (S4) st4 [r6] = r7, 4 Cycles * This is not real code Iterations 1 0S1 1 2S3 3S S1 S3S1 S4S3 S4S3 S4 567 S1 S3S1 S4S3 S4S3 S4 prologue kernel epilogue

27 Loop Optimization: Software Pipelining Code 27 ld4r4 = [r5], 4 ;; // load x[1] ld4r4 = [r5], 4 ;; // load x[2] addr7 = r4, r9 // y[1] = x[1]+ k ld4r4 = [r5], 4 ;; // load x[3] L1: ld4r4 = [r5], 4 // load x[i+3] add r7 = r4, r9 // y[i+1] = x[i+1] + k st4[r6] = r7, 4 // store y[i] br.cloop L1 ;; st4[r6] = r7, 4 // store y[n-2] addr7 = r4, r9 ;; // y[n-1] = x[n-1] + k st4 [r6] = r7, 4 // store y[n-1] add r7 = r4,r9 ;; // y[n] = x[n] + k st4[r6] = r7, 4 // store y[n] prologue kernel epilogue

28 Software Pipelining and Data Dependencies. 28 void f(int *p, int *q, int N){ int t, c; for(c=0 ; c

29 Software Pipelining and Data Dependencies. 29 void f(int *p, int *q, int N){ int t, c; for(c=0 ; c

30 Software Pipelining and Data Dependencies. 30 void f(int *p, int *q, int N){ int t, c; for(c=0 ; c

31 Software Pipelining and Data Dependencies. 31 void f(int *p, int *q, int N){ int t, c; for(c=0 ; c

32 Simulating an Infinite Register File 32 prolog: ldl r32 ← [r12]+ (rotate) r33 ← r32 ldl r32 ← [r12] add r34 ← 1 + r33 (rotate) r35 ← r34 (rotate) r34 ← r33 (rotate) r33 ← r32 loop: ldl r32 ← [r12]+ add r34 ← 1 + r33 stl [r13]+ ← r35 if(loop is not done) (rotate) temp ← r39 (rotate) r39 ← r38 (rotate) r38 ← r37 (rotate) r37 ← r36 (rotate) r36 ← r35 (rotate) r35 ← r34 (rotate) r34 ← r33 (rotate) r33 ← r32 (rotate) r32 ← temp goto loop epilog: add r34 ← 1 + r33 stl [r13]+ ← r35 (rotate) r35 ← r34 stl [r13]+ ← r35 void f(int *p, int *q, int N){ int t, c; for(c=0 ; c

33 Simulating an Infinite Register File 33 prolog: (1) ldl r32 ← [r12]+ (0) add r34 ← 1 + r33 (0) stl [r13]+ ← r35 (rotate all) (1) ldl r32 ← [r12]+ (1) add r34 ← 1 + r33 (0) stl [r13]+ ← r35 (rotate all) loop: (1) ldl r32 ← [r12]+ (1) add r34 ← 1 + r33 (1) stl [r13]+ ← r35 if(loop is not done) (rotate all) goto loop void f(int *p, int *q, int N){ int t, c; for(c=0 ; c

34 Simulating an Infinite Register File 34 loop: (p16) ldl r32 ← [r12]+ (p17) add r34 ← 1 + r33 (p18) stl [r13]+ ← r35 if(loop is not done) (rotate all) goto loop void f(int *p, int *q, int N){ int t, c; for(c=0 ; c

35 Support for Software Pipelining in the IA After a loop is converted into a software pipeline, it looks quite different from the original loop, Intel adopts the following terminology: source loop and source iteration: refer to the original source code kernel loop and kernel iteration: refer to the code that implements the software pipeline.

36 Loop Support in the IA-64: Register Rotation 36 The IA-64 has a rotating register base (rrb) register that is decremented by special software pipelined loop branches. When the rrb is decremented the valued stored in register X appear to move to register X+1, and the value of the highest numbered rotating register appears to move to the lowest numbered rotating register.

37 Loop Support in the IA-64: Register Rotation What registers can rotate? – The predicate registers p16-p63; – The floating-point registers f32-f127; – A programable portion of the general registers: The function alloc can allocate 0, 8, 16, 24, …, 96 general registers as rotating registers The lowest numbered rotating register is r32. – There are three rrb: rrb.gr, rrb.fr rrb.pr 37

38 How Register Rotation Helps Software Pipeline 38 The concept of a software pipelining branch: L1: ld4 r35 = [r4], 4// post-increment by 4 st4[r5] = r37, 4// post-increment by 4 swp_branch L1 ;; The pseudo-instruction swp_branch in the example rotates the general registers. Therefore the value stored into r35 is read in r37 two kernel iterations (and two rotations) later. The register rotation eliminated a dependence between the load and the store instructions, and allowed the loop to execute in one cycle.

39 How Register Rotation Helps Software Pipeline 39 The concept of a software pipelining branch: L1: ld4 r35 = [r4], 4// post-increment by 4 st4[r5] = r37, 4// post-increment by 4 swp_branch L1 ;; 7 R32 R33 R35 R34 R36 R37 R38 R39 0 RRB Physical Logical R35 R R32 R33 R35 R34 R36 R37 R38 R39 RRB Physical Logical R35 R R32 R33 R35 R34 R36 R37 R38 R39 -2 RRB Physical Logical R35 R37

40 The stage predicate 40 (S1): (p16) ld4 r4 = [r5], 4 (S2): (p17) (S3): (p18) addr7 = r4, r9 (S4): (p19) st4 [r6] = r7, 4 When assembling a software pipeline the programmer can assign a stage predicate to each stage of the pipeline to control the execution of the instructions in that stage. p16 is architecturally defined as the predicate for the first stage, p17 for the second, and so on. The software pipeline branch rotates the predicate registers and injects a 1 in p16. Thus enabling one stage of the pipeline at a time for the execution of the prolog.

41 The stage predicate 41 (S1): (p16) ld4 r4 = [r5], 4 (S2): (p17) (S3): (p18) addr7 = r4, r9 (S4): (p19) st4 [r6] = r7, 4 When the kernel counter reaches zero, the software pipeline branch starts to decrement the epilog counter and injects 0 in p16 at every rotation to execute the epilogue of the software pipelined loop.

42 Anatomy of a Software Pipelining Branch 42 LC? PR[16]=1 RRB-- branch PR[16]=0RRB-- PR[16]=0 RRB-- fall-thru EC? == 0 (epilog) EC-- >1 EC-- =1 EC =0 LC--  0 (prolog/kernel) special unrolled loops

43 Software Pipelining Example in the IA mov pr.rot= 0// Clear all rotating predicate registers cmp.eq p16,p0 = r0,r0// Set p16=1 mov ar.lc= 4// Set loop counter to n-1 mov ar.ec= 3// Set epilog counter to 3 … loop: (p16)ldl r32 = [r12], 1// Stage 1: load x (p17)add r34 = 1, r33// Stage 2: y=x+1 (p18)stl [r13] = r35,1// Stage 3: store y br.ctop loop // Branch back

44 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x General Registers (Physical) Predicate Registers 4 LC 3 EC x4 x5 x1 x2 x3 Memory General Registers (Logical) 0 RRB

45 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 4 LC 3 EC x4 x5 x1 x2 x3 Memory x General Registers (Physical) General Registers (Logical) 0 RRB

46 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 4 LC 3 EC x4 x5 x1 x2 x3 Memory x General Registers (Physical) General Registers (Logical) 0 RRB

47 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 4 LC 3 EC 1 x4 x5 x1 x2 x3 Memory x General Registers (Physical) General Registers (Logical) RRB

48 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 3 LC 3 EC x4 x5 x1 x2 x3 Memory x General Registers (Physical) General Registers (Logical) RRB

49 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 3 LC 3 EC x4 x5 x1 x2 x3 Memory x General Registers (Physical) General Registers (Logical) x2 RRB

50 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 3 LC 3 EC x4 x5 x1 x2 x3 Memory x General Registers (Physical) General Registers (Logical) x2 y1 RRB

51 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 3 LC 3 EC x4 x5 x1 x2 x3 Memory x General Registers (Physical) General Registers (Logical) x2 y1 RRB

52 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 3 LC 3 EC x4 x5 x1 x2 x3 Memory x General Registers (Physical) General Registers (Logical) x2 y1 RRB

53 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 2 LC 3 EC 1 x4 x5 x1 x2 x3 Memory x General Registers (Physical) General Registers (Logical) x2 y1 -2 RRB

54 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 2 LC 3 EC x4 x5 x1 x2 x3 Memory x General Registers (Physical) General Registers (Logical) x2y1x3 -2 RRB

55 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop y Predicate Registers 2 LC 3 EC x4 x5 x1 x2 x3 Memory General Registers (Physical) General Registers (Logical) x2y1x3 -2 RRB

56 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 2 LC 3 EC x4 x5 x1 x2 x3 y1 Memory y General Registers (Physical) General Registers (Logical) x2y1x3 -2 RRB

57 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 2 LC 3 EC x4 x5 x1 x2 x3 y1 Memory y General Registers (Physical) General Registers (Logical) x2y1x3 -2 RRB

58 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 1 LC 3 EC 1 x4 x5 x1 x2 x3 y1 Memory -3 RRB y General Registers (Physical) General Registers (Logical) x2y1x3

59 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 1 LC 3 EC x4 x5 x1 x2 x3 y1 Memory -3 RRB y2x General Registers (Physical) General Registers (Logical) x2y1x3

60 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 1 LC 3 EC x4 x5 x1 x2 x3 y1 Memory y2x General Registers (Physical) General Registers (Logical) y3y1x3 -3 RRB

61 Software Pipelining Example in the IA loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop Predicate Registers 1 LC 3 EC x4 x5 x1 x2 x3 y1 y2 Memory y2x General Registers (Physical) General Registers (Logical) y3y1x3 -3 RRB

62 Software Pipelining Example in the IA Predicate Registers 1 LC 3 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y1 y2 Memory y2x General Registers (Physical) General Registers (Logical) y3y1x3 -3 RRB

63 Software Pipelining Example in the IA Predicate Registers 0 LC 3 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop 1 x4 x5 x1 x2 x3 y1 y2 Memory -4 RRB y2x General Registers (Physical) General Registers (Logical) y3y1x3

64 Software Pipelining Example in the IA Predicate Registers 0 LC 3 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y1 y2 Memory y2 x5x General Registers (Physical) General Registers (Logical) y3y1x3 -4 RRB

65 Software Pipelining Example in the IA Predicate Registers 0 LC 3 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y1 y2 Memory y2x5x General Registers (Physical) General Registers (Logical) y3y1y4 -4 RRB

66 Software Pipelining Example in the IA Predicate Registers 0 LC 3 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y1 y2 y3 Memory -4 RRB y2x5x General Registers (Physical) General Registers (Logical) y3y1y4

67 Software Pipelining Example in the IA Predicate Registers 0 LC 3 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y1 y2 y3 Memory y2 x5x General Registers (Physical) General Registers (Logical) y3y1y4 -4 RRB

68 Software Pipelining Example in the IA Predicate Registers 0 LC 2 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop 0 x4 x5 x1 x2 x3 y1 y2 y3 Memory y2 x5x General Registers (Physical) General Registers (Logical) y3y1y4 -5 RRB

69 Software Pipelining Example in the IA Predicate Registers 0 LC 2 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop 0 x4 x5 x1 x2 x3 y1 y2 y3 Memory y2 x5x General Registers (Physical) General Registers (Logical) y3y1y4 -5 RRB

70 Software Pipelining Example in the IA Predicate Registers 0 LC 2 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y1 y2 y3 Memory y2x5x General Registers (Physical) General Registers (Logical) y3y1y4 -5 RRB

71 Software Pipelining Example in the IA Predicate Registers 0 LC 2 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y1 y2 y3 Memory y2x5y General Registers (Physical) General Registers (Logical) y3y1y4 -5 RRB

72 Software Pipelining Example in the IA Predicate Registers 0 LC 2 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y4 y1 y2 y3 Memory y2x5y General Registers (Physical) General Registers (Logical) y3y1y4 -5 RRB

73 Software Pipelining Example in the IA Predicate Registers 0 LC 2 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y4 y1 y2 y3 Memory y2x5y General Registers (Physical) General Registers (Logical) y3y1y4 -5 RRB

74 Software Pipelining Example in the IA Predicate Registers 0 LC 1 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop 0 x4 x5 x1 x2 x3 y4 y1 y2 y3 Memory y2x5y General Registers (Physical) General Registers (Logical) y3y1y4 -6 RRB

75 Software Pipelining Example in the IA Predicate Registers 0 LC 1 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y4 y1 y2 y3 Memory y2x5y General Registers (Physical) General Registers (Logical) y3y1y4 -6 RRB

76 Software Pipelining Example in the IA Predicate Registers 0 LC 1 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y4 y1 y2 y3 Memory y2x5y General Registers (Physical) General Registers (Logical) y3y1y4 -6 RRB

77 Software Pipelining Example in the IA Predicate Registers 0 LC 1 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y4 y5 y1 y2 y3 Memory y2x5y General Registers (Physical) General Registers (Logical) y3y1y4 -6 RRB

78 Software Pipelining Example in the IA Predicate Registers 0 LC 1 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y4 y5 y1 y2 y3 Memory y2x5y General Registers (Physical) General Registers (Logical) y3y1y4 -6 RRB

79 Software Pipelining Example in the IA Predicate Registers 0 LC 1 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop x4 x5 x1 x2 x3 y4 y5 y1 y2 y3 Memory y2x5y General Registers (Physical) General Registers (Logical) y3y1y4 -6 RRB

80 Software Pipelining Example in the IA Predicate Registers 0 LC 0 EC loop: (p16)ldl r32 = [r12], 1 (p17)add r34 = 1, r33 (p18)stl [r13] = r35,1 br.ctop loop 0 x4 x5 x1 x2 x3 y4 y5 y1 y2 y3 Memory y2x5y General Registers (Physical) General Registers (Logical) y3y1y4 -7 RRB


Download ppt "The IA-64 Architectural Innovations Hardware Support for Software Pipelining José Nelson Amaral 1."

Similar presentations


Ads by Google