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Ideal Junction Theory Assumptions Ex = 0 in the chg neutral reg. (CNR)

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Presentation on theme: "Ideal Junction Theory Assumptions Ex = 0 in the chg neutral reg. (CNR)"— Presentation transcript:

1 Ideal Junction Theory Assumptions Ex = 0 in the chg neutral reg. (CNR)
MB statistics are applicable Neglect gen/rec in depl reg (DR) Low level injections apply so that dnp < ppo for -xpc < x < -xp, and dpn < nno for xn < x < xnc Steady State conditions ©rlc L10-16Feb2011

2 Forward Bias Energy Bands
Ev Ec EFi xn xnc -xpc -xp q(Vbi-Va) EFP EFN qVa x Imref, EFn Imref, EFp ©rlc L10-16Feb2011

3 Law of the junction (follow the min. carr.)
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4 Law of the junction (cont.)
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5 Law of the junction (cont.)
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6 Injection Conditions ©rlc L10-16Feb2011

7 Apply the Continuity Eqn in CNR
Ideal Junction Theory (cont.) Apply the Continuity Eqn in CNR ©rlc L10-16Feb2011

8 Ideal Junction Theory (cont.)
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9 Ideal Junction Theory (cont.)
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10 Excess minority carrier distr fctn
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11 Carrier Injection ln(carrier conc) ln Na ln Nd ln ni ~Va/Vt ln ni2/Na
xn -xpc ln(carrier conc) ln Na ln Nd ln ni ln ni2/Nd ln ni2/Na xnc x ~Va/Vt -xp ©rlc L10-16Feb2011

12 Minority carrier currents
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13 Evaluating the diode current
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14 Special cases for the diode current
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15 Ideal diode equation Assumptions: Current dens, Jx = Js expd(Va/Vt)
low-level injection Maxwell Boltzman statistics Depletion approximation Neglect gen/rec effects in DR Steady-state solution only Current dens, Jx = Js expd(Va/Vt) where expd(x) = [exp(x) -1] ©rlc L10-16Feb2011

16 Ideal diode equation (cont.)
Js = Js,p + Js,n = hole curr + ele curr Js,p = qni2Dp coth(Wn/Lp)/(NdLp) = qni2Dp/(NdWn), Wn << Lp, “short” = qni2Dp/(NdLp), Wn >> Lp, “long” Js,n = qni2Dn coth(Wp/Ln)/(NaLn) = qni2Dn/(NaWp), Wp << Ln, “short” = qni2Dn/(NaLn), Wp >> Ln, “long” Js,n << Js,p when Na >> Nd ©rlc L10-16Feb2011

17 Diffnt’l, one-sided diode conductance
Static (steady-state) diode I-V characteristic IQ Va VQ ©rlc L10-16Feb2011

18 Diffnt’l, one-sided diode cond. (cont.)
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19 Charge distr in a (1- sided) short diode
dpn Assume Nd << Na The sinh excess minority carrier distribution becomes linear for Wn << Lp dpn(xn)=pn0expd(Va/Vt) Total chg = Q’p = Q’p = qdpn(xn)Wn/2 Wn = xnc- xn dpn(xn) Q’p x xn xnc ©rlc L10-16Feb2011

20 Charge distr in a 1- sided short diode
dpn Assume Quasi-static charge distributions Q’p = Q’p = qdpn(xn)Wn/2 ddpn(xn) = (W/2)* {dpn(xn,Va+dV) - dpn(xn,Va)} dpn(xn,Va+dV) dpn(xn,Va) dQ’p Q’p x xn xnc

21 Cap. of a (1-sided) short diode (cont.)

22 General time- constant
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23 General time- constant (cont.)
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24 General time- constant (cont.)
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25 References *Fundamentals of Semiconductor Theory and Device Physics, by Shyh Wang, Prentice Hall, 1989. **Semiconductor Physics & Devices, by Donald A. Neamen, 2nd ed., Irwin, Chicago. M&K = Device Electronics for Integrated Circuits, 3rd ed., by Richard S. Muller, Theodore I. Kamins, and Mansun Chan, John Wiley and Sons, New York, 2003. 1Device Electronics for Integrated Circuits, 2 ed., by Muller and Kamins, Wiley, New York, 1986. 2Physics of Semiconductor Devices, by S. M. Sze, Wiley, New York, 1981. 3 Physics of Semiconductor Devices, Shur, Prentice-Hall, 1990. ©rlc L10-16Feb2011


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