1. indDG: A New Model for Independent Double-Gate MOSFET Santanu Mahapatra Nano-Scale Device Research Lab Indian Institute of Science Bangalore Email: santanu@cedt.iisc.ernet.in Web: http://www.cedt.iisc.ernet.in/nanolab/

2. Outline Common versus Independent double gate Development of indDG Core Single Implicit Equation based IVE Solution Technique for IVE Charge Model Extension to Tri-Gate SPICE Implementation Future Works

3. Common vs Independent DG MOSFET (1) Courtesy: Endo et al. IEEE EDL 2009

4. Common vs Independent DG MOSFET (2) With IDG MOSFET the design space gets extended from 2D to 3D, which leads to novel circuit design possibilities e.g., 1.High density reduced stack logic, IEEE T-ED 2006 2.Compact sequential circuit, IEEE T-ED 2006 3.Mixer, IEEE T-ED 2005 4.SRAM, IEEE EDL 2009 V g1 V ds V g2 Dynamic Threshold Voltage Control: Use one gate to drive, other gate to V th control

5. Development of indDG Core Single Implicit Equation Based IVE (1) A Very Complex Problem Requires Solution of COUPLED implicit equations which has DISCONTINUITY!! Previous solution (Taur, and then Gildenblat) SDG device has symmetric BC, that leads to additional implied BC (electric field =0 at y=0), which results in very simple trigonometric IVE

6. Development of indDG Core Single Implicit Equation Based IVE (2) By indigenous handling of BC, we introduced single implicit equation based IVE that is 5x faster than coupled IVE. Sahoo et al., IEEE T-ED, V 57, N 3, 2010

7. Development of indDG Core Solution technique for IVE (1) Discontinuity @ G = 0 for both Trig and Hyp IVE Singularity @ γ = π for Trig IVE Conventional NR method doesnt GUARANTEE convergence!!

8. Development of indDG Core Solution technique for IVE (1) We use RBM (Root Bracketing Method) instead of NR-based method to achieve guaranteed convergence. We did a rigorous study of all RBMs available in the literatures (~20). And finally choose LZ4 technique (D. Le, ACM T-MS 1985) to solve the IVEs. But RBM requires solution space…. So we need to solve ONE more implicit equation, to find the solution space for Trig/Hyp IVE. We do some smart optimization of solution space to improve overall computational efficiency. And so we need to solve THREE implicit equations SEQUENCIALLY (one to choose mode, one to find solution space and finally the main IVE) to calculate the surface potential. Srivatsava et al., IEEE T-ED, V 58, N 6, 2011 Abraham et al., IEEE T-ED, April, 2012

9. Development of indDG Core The Charge Model : Issues with existing Model THREE MODES OF OPERATION T HH TH Line: Model (G. Dessai, IEEE T-ED 2010) Symbol : Numerical

10. Development of indDG Core The Charge Model: Charge linearization Concept As the exact solution of the integrals are not available charge linearization techniques are introduced over the years to approximate F as quadratic function of surface potentials (or charge densities) so that closed form expressions for terminal charges are obtained.

11. Development of indDG Core The Charge Model : The NLF Factor To approximate F as quadratic function of ψ 1 or ψ 2 (Q i1 or Q i2 ), they should hold linear-relationship along the channel for a given bias condition.

12. Development of indDG Core The Charge Model: Piecewise Linearization Technique We segment the channel, so that for each segment ψ 1 holds linear relationship with ψ 2 so that conventional charge linearization technique could be applied to formulate the Terminal Charges. Srivatsava et al., Appearing in IEEE T-ED, 2012

13. Development of indDG Core The Charge Model: Comparison of linearization indDG charge model is based on the relationship of the surface potentials It is derivative free and thus numerically robust

14. SDG with small Tox asymmetry (indDG-c) There will always be some amount of asymmetry between the gate oxide thicknesses due to process variation and uncertainties indDG-c handles the asymmetry as it is based on the relationship between surface potential (which is linear for this case) We use an accurate analytical approximation of surface potential by novel perturbation technique Srivatsava et al., IEEE T-ED, April, 2012 Simple closed form function of Bias and device parameters, derived from the IDG IVEs

15. Including Body Doping Tox1=Tox2=1nm; Tsi = 20nmTox1=1nm Tox2=1.5nm Tsi = 10nm

16. Tri Gate Extension Tri Gate MOSFET cannot be model like Bulk or DG as the 3D Poisson Equation cannot be approximated as 1D Poisson for long channel cases. Models for Tri Gate are developed on top of the planner DG Models

17. Model Implementation Model is implemented in Silvaco SmartSpice through Verilog-A interface S/D Symmetry of Terminal Charge 101 Stage Ring Oscillator Also successfully simulated 8-bit Ripple carry adder, Jhonson Counter

18. Future Plans To include Small geometry effects, NQS, Noise, extrinsic elements to make it applicable for practical devices…

19. Acknowledgement My Masters and Ph.D. students Department of Science and Technology (DST), Government of India Dr. Ivan Pesic and his team @ Silvaco International