1. 1 © 2009 Universität Karlsruhe (TH), System Architecture Group Priority Inversion

2. © 2009 Universität Karlsruhe (TH), System Architecture Group 2 Roadmap for Today Priority Inversion Resource protocols Synchronization Mechanisms Signaling Semaphores Monitors Synchronization Problems Producer / Consumer and Reader / Writer

3. © 2009 Universität Karlsruhe (TH), System Architecture Group 3 Example 5 processes process number equals priority Priority of P5 > priority of P1 Release and execution times as shown No deadlines (only an example for later comparison) Priority-driven preemptively scheduled 02410681214201816 P1 P2 P3 P4 P5

4. © 2009 Universität Karlsruhe (TH), System Architecture Group 4 Example 02410681214201816 P1 P2 P3 P4 P5

5. © 2009 Universität Karlsruhe (TH), System Architecture Group 5 Example 02410681214201816 P1 P2 P3 P4 P5

6. © 2009 Universität Karlsruhe (TH), System Architecture Group 6 Example 02410681214201816 P1 P2 P3 P4 P5

7. © 2009 Universität Karlsruhe (TH), System Architecture Group 7 Example 02410681214201816 P1 P2 P3 P4 P5

8. © 2009 Universität Karlsruhe (TH), System Architecture Group 8 Example 02410681214201816 P1 P2 P3 P4 P5

9. © 2009 Universität Karlsruhe (TH), System Architecture Group 9 Example 02410681214201816 P1 P2 P3 P4 P5

10. © 2009 Universität Karlsruhe (TH), System Architecture Group 10 Example 02410681214201816 P1 P2 P3 P4 P5

11. © 2009 Universität Karlsruhe (TH), System Architecture Group 11 Example 02410681214201816 P1 P2 P3 P4 P5

12. © 2009 Universität Karlsruhe (TH), System Architecture Group 12 Example 02410681214201816 P1 P2 P3 P4 P5

13. © 2009 Universität Karlsruhe (TH), System Architecture Group 13 Example 02410681214201816 P1 P2 P3 P4 P5

14. © 2009 Universität Karlsruhe (TH), System Architecture Group 14 Example 02410681214201816 P1 P2 P3 P4 P5

15. © 2009 Universität Karlsruhe (TH), System Architecture Group 15 Example 02410681214201816 P1 P2 P3 P4 P5

16. © 2009 Universität Karlsruhe (TH), System Architecture Group 16 Example 02410681214201816 P1 P2 P3 P4 P5

17. © 2009 Universität Karlsruhe (TH), System Architecture Group 17 Example 02410681214201816 P1 P2 P3 P4 P5

18. © 2009 Universität Karlsruhe (TH), System Architecture Group 18 Example 02410681214201816 P1 P2 P3 P4 P5

19. © 2009 Universität Karlsruhe (TH), System Architecture Group 19 Example 02410681214201816 P1 P2 P3 P4 P5

20. © 2009 Universität Karlsruhe (TH), System Architecture Group 20 Example 02410681214201816 P1 P2 P3 P4 P5

21. © 2009 Universität Karlsruhe (TH), System Architecture Group 21 Example 02410681214201816 P1 P2 P3 P4 P5

22. © 2009 Universität Karlsruhe (TH), System Architecture Group 22 Example 02410681214201816 P1 P2 P3 P4 P5

23. © 2009 Universität Karlsruhe (TH), System Architecture Group 23 Example 02410681214201816 P1 P2 P3 P4 P5

24. © 2009 Universität Karlsruhe (TH), System Architecture Group 24 Example 02410681214201816 P1 P2 P3 P4 P5

25. © 2009 Universität Karlsruhe (TH), System Architecture Group 25 Reality is more complex Processes are not usually independent

26. © 2009 Universität Karlsruhe (TH), System Architecture Group 26 Real-Time Traffic Scheduling Two process streams A high priority & a low priority

27. © 2009 Universität Karlsruhe (TH), System Architecture Group 27 Problem Intersection is a mutually exclusive resource

28. © 2009 Universität Karlsruhe (TH), System Architecture Group 28 Mutual Exclusion Can be solved by resource access protocols

29. 29 © 2009 Universität Karlsruhe (TH), System Architecture Group Priorities and Resource Contention Main Reference Pane W. S. Liu Real-time Systems, Chapter 8

30. © 2009 Universität Karlsruhe (TH), System Architecture Group 30 Resources Processes require resources in order to execute. (e.g. locks, ports, memory, …) Resource characteristics Serially reusable, Mutually exclusive We ignore resources that are infinitely available or exceed demand, or can be pre-allocated.

31. © 2009 Universität Karlsruhe (TH), System Architecture Group 31 Resource Contention Problem Priority inversion. We need to, at least, bound the length of priority inversion. Preferably minimize the length of priority inversion. P3P3 P2P2 P1P1 R1 3 2 1 Famous example of priority inversion: Mars Pathfinder 1997

32. © 2009 Universität Karlsruhe (TH), System Architecture Group 32 Marth Pathfinder Mars Path Finder and the famous Mars Rock YOGI

33. © 2009 Universität Karlsruhe (TH), System Architecture Group 33 Resource Contention Problems Timing anomaly Deadlock P2P2 P1P1 R2R2 2 1 R1R1

34. © 2009 Universität Karlsruhe (TH), System Architecture Group 34 Major Assumption Single processor system Resource Contention

35. © 2009 Universität Karlsruhe (TH), System Architecture Group 35 Our Example + 2 Resources 02410681214201816 Resource 1 Resource 2 Nested Critical Section * * P2 first needs R1 and then later additionally R2 Example with Resources P5 P4 P3 P2 P1

36. © 2009 Universität Karlsruhe (TH), System Architecture Group 36 Simple Priority Driven Scheduling 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

37. © 2009 Universität Karlsruhe (TH), System Architecture Group 37 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

38. © 2009 Universität Karlsruhe (TH), System Architecture Group 38 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

39. © 2009 Universität Karlsruhe (TH), System Architecture Group 39 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

40. © 2009 Universität Karlsruhe (TH), System Architecture Group 40 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

41. © 2009 Universität Karlsruhe (TH), System Architecture Group 41 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

42. © 2009 Universität Karlsruhe (TH), System Architecture Group 42 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

43. © 2009 Universität Karlsruhe (TH), System Architecture Group 43 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

44. © 2009 Universität Karlsruhe (TH), System Architecture Group 44 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

45. © 2009 Universität Karlsruhe (TH), System Architecture Group 45 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

46. © 2009 Universität Karlsruhe (TH), System Architecture Group 46 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

47. © 2009 Universität Karlsruhe (TH), System Architecture Group 47 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

48. © 2009 Universität Karlsruhe (TH), System Architecture Group 48 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

49. © 2009 Universität Karlsruhe (TH), System Architecture Group 49 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

50. © 2009 Universität Karlsruhe (TH), System Architecture Group 50 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

51. © 2009 Universität Karlsruhe (TH), System Architecture Group 51 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

52. © 2009 Universität Karlsruhe (TH), System Architecture Group 52 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

53. © 2009 Universität Karlsruhe (TH), System Architecture Group 53 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

54. © 2009 Universität Karlsruhe (TH), System Architecture Group 54 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

55. © 2009 Universität Karlsruhe (TH), System Architecture Group 55 Example 02410681214201816 SPD Scheduling P5 P4 P3 P2 P1

56. © 2009 Universität Karlsruhe (TH), System Architecture Group 56 Result The most important processes P5 and P4 are heavily delayed P3 is almost not delayed due to its characteristic, it does not need any resource Find a better solution SPD Scheduling

57. © 2009 Universität Karlsruhe (TH), System Architecture Group 57 4 Resource Allocation Protocols Non Preemptive Critical Sections (NPCS) Priority Inheritance (PI) Priority-Ceiling Protocol (PCP) Stacked Priority-Ceiling Protocol (SPCP) … and some others See text book (Liu) Resource Allocation Protocols

58. © 2009 Universität Karlsruhe (TH), System Architecture Group 58 Nonpreemptive Critical Sections As soon as a process holds a resource it is no longer preemptable * Prevents deadlock Bounds priority inversion Max blocking time is the maximum execution time of the critical sections of all lower priority processes P3 P2 P1 R1 3 2 1 * This process gets highest priority in system 3 NPCS Scheduling max prio cannot happen at t1 Allocate at t0

59. © 2009 Universität Karlsruhe (TH), System Architecture Group 59 Non-Preemptive Critical Sections 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

60. © 2009 Universität Karlsruhe (TH), System Architecture Group 60 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

61. © 2009 Universität Karlsruhe (TH), System Architecture Group 61 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

62. © 2009 Universität Karlsruhe (TH), System Architecture Group 62 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

63. © 2009 Universität Karlsruhe (TH), System Architecture Group 63 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

64. © 2009 Universität Karlsruhe (TH), System Architecture Group 64 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

65. © 2009 Universität Karlsruhe (TH), System Architecture Group 65 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

66. © 2009 Universität Karlsruhe (TH), System Architecture Group 66 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

67. © 2009 Universität Karlsruhe (TH), System Architecture Group 67 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

68. © 2009 Universität Karlsruhe (TH), System Architecture Group 68 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

69. © 2009 Universität Karlsruhe (TH), System Architecture Group 69 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

70. © 2009 Universität Karlsruhe (TH), System Architecture Group 70 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

71. © 2009 Universität Karlsruhe (TH), System Architecture Group 71 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

72. © 2009 Universität Karlsruhe (TH), System Architecture Group 72 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

73. © 2009 Universität Karlsruhe (TH), System Architecture Group 73 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

74. © 2009 Universität Karlsruhe (TH), System Architecture Group 74 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

75. © 2009 Universität Karlsruhe (TH), System Architecture Group 75 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

76. © 2009 Universität Karlsruhe (TH), System Architecture Group 76 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

77. © 2009 Universität Karlsruhe (TH), System Architecture Group 77 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

78. © 2009 Universität Karlsruhe (TH), System Architecture Group 78 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

79. © 2009 Universität Karlsruhe (TH), System Architecture Group 79 Example 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

80. © 2009 Universität Karlsruhe (TH), System Architecture Group 80 Comparison with SPD-Scheduling 02410681214201816 NPCS Scheduling P5 P4 P3 P2 P1

81. © 2009 Universität Karlsruhe (TH), System Architecture Group 81 Analysis: Nonpreemptive Critical Sections Pros Simple No prior knowledge of resource requirements needed Prevents deadlock Cons Low priority process blocks high priority process even when there are no resource conflicts Protocol only suitable for trusted software Usually implemented by interrupt disabling In CS there is no system calls otherwise CPU wasting in case of a blocking system call NPCS Scheduling

82. © 2009 Universität Karlsruhe (TH), System Architecture Group 82 Worst-Case Blocking Time Longest lower-priority critical section: bt = blocking time cst = critical section time bt i (rc) = max {cst k } i+1 k n NPCS Scheduling Not that realistic

83. © 2009 Universität Karlsruhe (TH), System Architecture Group 83 Priority Inheritance (PI) When a high-priority process (P3) blocks, the low-priority process (P1) inherits the current priority of the blocking process PI bounds priority inversion 1 P3 P2 P1 R1 3 2 3 PI Scheduling

84. © 2009 Universität Karlsruhe (TH), System Architecture Group 84 Example with Priority Inheritance 02410681214201816 PI Scheduling P5 P4 P3 P2 P1

85. © 2009 Universität Karlsruhe (TH), System Architecture Group 85 Example with Priority Inheritance 02410681214201816 PI Scheduling P5 P4 P3 P2 P1

86. © 2009 Universität Karlsruhe (TH), System Architecture Group 86 Example with Priority Inheritance 02410681214201816 PI Scheduling P5 P4 P3 P2 P1

87. © 2009 Universität Karlsruhe (TH), System Architecture Group 87 Example with Priority Inheritance 02410681214201816 PI Scheduling P5 P4 P3 P2 P1

88. © 2009 Universität Karlsruhe (TH), System Architecture Group 88 Example with Priority Inheritance 02410681214201816 PI Scheduling P5 P4 P3 P2 P1

89. © 2009 Universität Karlsruhe (TH), System Architecture Group 89 Example with Priority Inheritance 02410681214201816 PI Scheduling P5 P4 P3 P2 P1

90. © 2009 Universität Karlsruhe (TH), System Architecture Group 90 Example with Priority Inheritance 02410681214201816 PI Scheduling P5 P4 P3 P2 P1

91. © 2009 Universität Karlsruhe (TH), System Architecture Group 91 Example with Priority Inheritance 02410681214201816 4 PI Scheduling P5 P4 P3 P2 P1

92. © 2009 Universität Karlsruhe (TH), System Architecture Group 92 Example with Priority Inheritance 02410681214201816 4 PI Scheduling P5 P4 P3 P2 P1

93. © 2009 Universität Karlsruhe (TH), System Architecture Group 93 Example with Priority Inheritance 02410681214201816 5 4 PI Scheduling P5 P4 P3 P2 P1

94. © 2009 Universität Karlsruhe (TH), System Architecture Group 94 Example with Priority Inheritance 02410681214201816 5 45 PI Scheduling P5 P4 P3 P2 P1

95. © 2009 Universität Karlsruhe (TH), System Architecture Group 95 Example with Priority Inheritance 02410681214201816 5 45 PI Scheduling P5 P4 P3 P2 P1

96. © 2009 Universität Karlsruhe (TH), System Architecture Group 96 Example with Priority Inheritance 02410681214201816 5 451 PI Scheduling P5 P4 P3 P2 P1

97. © 2009 Universität Karlsruhe (TH), System Architecture Group 97 Example with Priority Inheritance 02410681214201816 5 451 PI Scheduling P5 P4 P3 P2 P1

98. © 2009 Universität Karlsruhe (TH), System Architecture Group 98 Example with Priority Inheritance 02410681214201816 5 451 PI Scheduling P5 P4 P3 P2 P1

99. © 2009 Universität Karlsruhe (TH), System Architecture Group 99 Example with Priority Inheritance 02410681214201816 52 451 PI Scheduling P5 P4 P3 P2 P1

100. © 2009 Universität Karlsruhe (TH), System Architecture Group 100 Example with Priority Inheritance 02410681214201816 52 451 PI Scheduling P5 P4 P3 P2 P1

101. © 2009 Universität Karlsruhe (TH), System Architecture Group 101 Example with Priority Inheritance 02410681214201816 52 451 PI Scheduling P5 P4 P3 P2 P1

102. © 2009 Universität Karlsruhe (TH), System Architecture Group 102 Example with Priority Inheritance 02410681214201816 52 451 PI Scheduling P5 P4 P3 P2 P1

103. © 2009 Universität Karlsruhe (TH), System Architecture Group 103 Example with Priority Inheritance 02410681214201816 52 451 PI Scheduling P5 P4 P3 P2 P1

104. © 2009 Universität Karlsruhe (TH), System Architecture Group 104 Example with Priority Inheritance 02410681214201816 52 451 PI Scheduling P5 P4 P3 P2 P1

105. © 2009 Universität Karlsruhe (TH), System Architecture Group 105 Example with Priority Inheritance 02410681214201816 52 451 PI Scheduling P5 P4 P3 P2 P1

106. © 2009 Universität Karlsruhe (TH), System Architecture Group 106 Example with Priority Inheritance 02410681214201816 52 451 PI Scheduling P5 P4 P3 P2 P1

107. © 2009 Universität Karlsruhe (TH), System Architecture Group 107 Comparison with SPD Rule 02410681214201816 52 451 PI Scheduling P5 P4 P3 P2 P1

108. © 2009 Universität Karlsruhe (TH), System Architecture Group 108 Analysis: Priority Inheritance Pros Prevents uncontrolled priority inversion. Needs no knowledge of resource requirements. Cons Does not prevent deadlock. Does not minimise blocking times. With chained blocking, worst-case blocking time is min(n,m) critical sections n = number of lower priority processes that can block P m = number of resources that can be used to block P Some overhead in a release or acquire operation PI Scheduling

109. © 2009 Universität Karlsruhe (TH), System Architecture Group 109 Chained Blocking 4 lower priority processes 4 potentially conflicting resources Worst-case blocking time = 16 units 1 Time Priority PI Scheduling 1 Assume lower priority process allocates its first resource just before higher priority process runs

110. © 2009 Universität Karlsruhe (TH), System Architecture Group 110 Priority Ceiling Protocol Avoids deadlock by defining an order of resource acquisition Prevents transitive (chained) blocking Worst-case blocking time = single critical section PCP Scheduling Description how to implement PCP, see: http://www.awprofessional.com/articles/article.asp?p=30188&seqNum=5&rl=1

111. © 2009 Universität Karlsruhe (TH), System Architecture Group 111 Priority Ceilings Resources required by all processes are known a priori Similar approach as with deadlock avoidance Priority ceiling of resource R i is equal to the highest priority of all processes that use R i Priority ceiling of system is highest priority ceiling of all resources currently in use PCP Scheduling

112. © 2009 Universität Karlsruhe (TH), System Architecture Group 112 Priority Ceilings of Our Example 02410681214201816 =5 =4 Priority Ceilings of Ri PCP Scheduling P5 P4 P3 P2 P1

113. © 2009 Universität Karlsruhe (TH), System Architecture Group 113 Priority Ceiling Protocol Rules Priority inheritance applies as before. When a process (P) requests a resource (R) either: If R is allocated P blocks (+ priority inheritance) If R is free, If Ps current priority > systems priority ceiling R is allocated to process P If Ps current priority systems priority ceiling P blocks – except if: P already holds a resource whose priority ceiling is equal to the systems priority ceiling PCP Scheduling

114. © 2009 Universität Karlsruhe (TH), System Architecture Group 114 Example 02410681214201816 curr max PCP Scheduling P5 P4 P3 P2 P1

115. © 2009 Universität Karlsruhe (TH), System Architecture Group 115 Example 02410681214201816 PCP Scheduling P5 P4 P3 P2 P1

116. © 2009 Universität Karlsruhe (TH), System Architecture Group 116 Example 02410681214201816 curr PCP Scheduling P5 P4 P3 P2 P1

117. © 2009 Universität Karlsruhe (TH), System Architecture Group 117 Example 02410681214201816 Prio(P2) < CurrSPC no allocation PCP Scheduling P5 P4 P3 P2 P1

118. © 2009 Universität Karlsruhe (TH), System Architecture Group 118 Example 02410681214201816 2 … but P1 inherits prio(P2) = 2 PCP Scheduling P5 P4 P3 P2 P1

119. © 2009 Universität Karlsruhe (TH), System Architecture Group 119 Example 02410681214201816 2 PCP Scheduling P5 P4 P3 P2 P1

120. © 2009 Universität Karlsruhe (TH), System Architecture Group 120 Example 02410681214201816 2 PCP Scheduling P5 P4 P3 P2 P1

121. © 2009 Universität Karlsruhe (TH), System Architecture Group 121 Example 02410681214201816 24 PCP Scheduling P5 P4 P3 P2 P1

122. © 2009 Universität Karlsruhe (TH), System Architecture Group 122 Example 02410681214201816 24 PCP Scheduling P5 P4 P3 P2 P1

123. © 2009 Universität Karlsruhe (TH), System Architecture Group 123 Example 02410681214201816 24 PCP Scheduling P5 P4 P3 P2 P1

124. © 2009 Universität Karlsruhe (TH), System Architecture Group 124 Example 02410681214201816 24 PCP Scheduling P5 P4 P3 P2 P1

125. © 2009 Universität Karlsruhe (TH), System Architecture Group 125 Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

126. © 2009 Universität Karlsruhe (TH), System Architecture Group 126 Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

127. © 2009 Universität Karlsruhe (TH), System Architecture Group 127 Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

128. © 2009 Universität Karlsruhe (TH), System Architecture Group 128 Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

129. © 2009 Universität Karlsruhe (TH), System Architecture Group 129 Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

130. © 2009 Universität Karlsruhe (TH), System Architecture Group 130 Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

131. © 2009 Universität Karlsruhe (TH), System Architecture Group 131 Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

132. © 2009 Universität Karlsruhe (TH), System Architecture Group 132 Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

133. © 2009 Universität Karlsruhe (TH), System Architecture Group 133 Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

134. © 2009 Universität Karlsruhe (TH), System Architecture Group 134 Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

135. © 2009 Universität Karlsruhe (TH), System Architecture Group 135 Comparison to Previous Example 02410681214201816 241 PCP Scheduling P5 P4 P3 P2 P1

136. © 2009 Universität Karlsruhe (TH), System Architecture Group 136 Analysis: Priority Ceiling Protocol Pros Avoids deadlocks If a process doesnt self suspend, a process is blocked at most once during execution Processes cannot be transitively blocked minimizes blocking time to the longest lower-priority conflicting critical section (+ context switches) Processes only receive their first resource when all required resources are not held by lower priority processes Cons A priori knowledge of resource needs is required PCP Scheduling

137. © 2009 Universität Karlsruhe (TH), System Architecture Group 137 Stack-Based Priority Ceiling Protocol The motivation is to share a single stack for all processes Saves stack space. Restriction: processes cannot self- suspend. SPCP Scheduling

138. © 2009 Universität Karlsruhe (TH), System Architecture Group 138 Rules Scheduling: After a process is released, it is blocked from starting until its assigned priority is higher than the current system priority ceiling. Unblocked processes are preemptively priority scheduled according to their assigned priority. Resource allocation: Whenever a process requests a resource it receives the resource. SPCP Scheduling

139. © 2009 Universität Karlsruhe (TH), System Architecture Group 139 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

140. © 2009 Universität Karlsruhe (TH), System Architecture Group 140 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

141. © 2009 Universität Karlsruhe (TH), System Architecture Group 141 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

142. © 2009 Universität Karlsruhe (TH), System Architecture Group 142 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

143. © 2009 Universität Karlsruhe (TH), System Architecture Group 143 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

144. © 2009 Universität Karlsruhe (TH), System Architecture Group 144 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

145. © 2009 Universität Karlsruhe (TH), System Architecture Group 145 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

146. © 2009 Universität Karlsruhe (TH), System Architecture Group 146 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

147. © 2009 Universität Karlsruhe (TH), System Architecture Group 147 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

148. © 2009 Universität Karlsruhe (TH), System Architecture Group 148 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

149. © 2009 Universität Karlsruhe (TH), System Architecture Group 149 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

150. © 2009 Universität Karlsruhe (TH), System Architecture Group 150 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

151. © 2009 Universität Karlsruhe (TH), System Architecture Group 151 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

152. © 2009 Universität Karlsruhe (TH), System Architecture Group 152 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

153. © 2009 Universität Karlsruhe (TH), System Architecture Group 153 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

154. © 2009 Universität Karlsruhe (TH), System Architecture Group 154 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

155. © 2009 Universität Karlsruhe (TH), System Architecture Group 155 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

156. © 2009 Universität Karlsruhe (TH), System Architecture Group 156 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

157. © 2009 Universität Karlsruhe (TH), System Architecture Group 157 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

158. © 2009 Universität Karlsruhe (TH), System Architecture Group 158 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

159. © 2009 Universität Karlsruhe (TH), System Architecture Group 159 Example 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

160. © 2009 Universität Karlsruhe (TH), System Architecture Group 160 Comparison with Priority Ceiling Protocol 02410681214201816 SPCP Scheduling P5 P4 P3 P2 P1

161. © 2009 Universität Karlsruhe (TH), System Architecture Group 161 Analysis: Stack-Based Priority Ceiling Pros Simple to implement. Slightly better worst-case when compared to normal PCP – two less context switches. No priority inheritance needed. Cons Threads cannot self suspend. SPCP Scheduling

162. © 2009 Universität Karlsruhe (TH), System Architecture Group 162 Summary 4 protocols controlling resource access in priority driven preemptive systems NPCS PI PCP SPCP Summary

163. © 2009 Universität Karlsruhe (TH), System Architecture Group 163 Summary NPCS and PI do not require a priori knowledge of resource requirements PI neither prevents deadlocks nor avoids deadlocks All protocols -except PI- ensure that processes are blocked at most once * Summary