Presentation is loading. Please wait.

Presentation is loading. Please wait.

Reporter :LYWang 2013.10.7. We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication.

Similar presentations


Presentation on theme: "Reporter :LYWang 2013.10.7. We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication."— Presentation transcript:

1 Reporter :LYWang

2 We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of RISC processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows more than one master to use the bus because of multiple channels. As a result of the test program, the proposed platform has better efficiency by 26.58% than the SoC platform with shared bus on-chip bus.

3 reduce design and verification time [1] improve SoC Network Architecture [2] open source soc debug interface [7][3][4][5][6] specification This paper: Design of Multimedia SoC Platform with a Crossbar On-chip Bus for Embedded Systems Solve bottleneck of communication Apply

4 What’s the problem:  Communication of multiple IPs is limited by the bottleneck on traditional shared bus. 。 When a master communicate with one slave, the other master can not communicate with other slave. Proposed method:  Crossbar on-chip bus 。 Multiple channel allows more than one master to use the bus. 。 The proposed platform will have better efficient.

5 Let host and AC97 code communicate with each other. 16 slave interface Select highest priority master 8 master interface Decode address from master Transmit request to slave interface OpenRISC 1200 Synthesizable CPU core IP core is implemented in VHDL Modify cache 1 way -> 4 way Check the sigmal between CPU and WISHBONE Let Graphic image display a computer hardware that translates data between parallel and serial

6 kj The system performance reduced when access requests to a shared communication resource.

7 Master interface contain 16 slave interface, 8 master interface

8 Block diagram of Master Inteface If master interface receives request from mater, it will decode the address and select the communication channel than send the request to slave interface.

9 Multiple channel architecture The multiple channel architecture is formed of WISHBONE protocol. Every of the master interface consists of 16 communication channels with the 16 slave interfaces

10 Master select controller When the slave interface receives a request from master. Master select controller will check the information value of master’s priority from register, and slave interface will connect to a slave according to the higher priority master.

11 If a request signal occurs from a master, the priority selector will take priority information from the register file, and compare it with the priority values of masters, and discriminate the highest priority value, and select the corresponding arbiter. The arbiter is formed of arbiter priority 0, arbiter priority 1, arbiter priority 2 and arbiter priority 3. 0 shows the lowest priority value, and 3 shows the highest priority value. Each arbiter operates as round robin system, and has the information of the master which has the corresponding priority value. It means that each of the arbiter remembers the last processed master, which has the corresponding priority value, and selects the next master in order. It prevents one master from occupying the bus for a long time. The arbiter is formed of arbiter priority 0, 1, 2 and 3. 0 shows the lowest priority value, and 3 shows the highest priority value. Each arbiter operates as round robin system, and has the information of the last processed master which has the corresponding priority value It prevents one master from occupying bus for a long time.

12 Table 1 shows the order of the communication between the 5 masters and slave 0, when the master 0's priority value is set to 3 and the master 1, 2, 3, 4's priority values are set to 1 and the five masters send request signals to the slave interface. ‘↓’ sign means there is a communication. In shared bus system, two masters occupy the bus, but in multiple channel bus, masters communicate with slave 0 equally except for the master 0 with the higher priority. In other words, high priority master occupies the bus continuously in previous shared bus system, because it divided into eight priorities, but multiple channel bus divides the priority value to 4 steps. The masters, which have the same priority, are granted with round robin method, and minimize one of the masters exclusive occupation on the bus, and make an efficient and balanced communication happen. The register file has sixteen 16-bit registers, and each 16-bit register is mapped to each of the sixteen slaves(0∼15). It offers priority value of eight masters with 2 bits. The 16-bit value, which is saved to register, could be saved with different values by user. Each slave sets high priority to several masters which need to process quickly. Therefore it makes efficient communicati on. 5 masters and 1 slave master 0's priority value is set to 3 and the master 1, 2, 3, 4's priority values are set to 1 five masters send request signals to the slave interface

13 Let multiple master send request to multiple slave. Compare shared bus with crossbar bus.

14 Test 1 : The VGA controller reads video data from the SRAM while the RISC processor is fetching the instruction Test 2 : The processor accesses to the UART when VGA controller accesses to the SRAM and the processor accesses to the FLASH memory

15 Test 1 : The VGA controller reads video data from the SRAM while the RISC processor is fetching the instruction Test 2 : The processor accesses to the UART when VGA controller accesses to the SRAM and the processor accesses to the FLASH memory

16 Conclusion  Propose multimedia SoC platform for a multiple on-chip communication and performance improvement.  The proposed SoC platform shows better efficiency by 26.58% than the SoC platform with shared on-chip bus. My comment  Learn what’s the limit of shared bus and the good prospects of crossbar bus.  This paper do not introduce crossbar bus internal structure.

17

18

19 ProcessABCDE 到達時間 服務時間 (T s ) quantum = 1


Download ppt "Reporter :LYWang 2013.10.7. We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication."

Similar presentations


Ads by Google