2 Programmable Logic Families Structured ASICHardCopy® II, HardCopy StratixHigh & Medium Density FPGAsStratix II, Stratix, APEX™ II, APEX 20K, & FLEX 10K®Low-Cost FPGAsCyclone II & CycloneFPGAs with Clock Data RecoveryStratix II GXCPLDsMAX II, MAX 7000 & MAX 3000Embedded Processor SolutionsNios IIConfiguration DevicesSerial (EPCS) & Enhanced (EPC)
3 MAX 7000A & MAX 3000A Family Overview ParameterMAX 3000AMAX 7000AEPM3032AEPM3064AEPM3128AEPM3256AEPM3512AEPM7032AEEPM7064AEEPM7128AEEPM7256AEEPM7512AEUseable GatesMacrocellsMaximum User I/O PinstPD (ns)fCNT (MHz)tSU (ns)tCO1 (ns)60032344.52272.93.01,25064664.52222.83.12,500128965.01923.33.45,0002561587.51275.24.810,0005122087.51165.64.760032364.52272.93.01,25064684.52222.83.12,5001281005.01923.33.45,0002561645.51723.93.510,0005122127.51165.64.7
4 Complete Voltage Portfolio MAX 7000SMAX 7000AEMAX 7000BPerformance LeaderFeature LeaderWide Range of Package OfferingsIndustrial-Grade OfferingsHigh PerformanceFeature LeaderWide Range of Package OfferingsHigh PerformanceFeature LeaderWide Range of Package OfferingsMAX 3000APrice LeaderFeature & Package Subset of MAX 7000AE
6 MAX Macrocell Parallel Logic Expanders (from other MCs) Programmable GlobalClearGlobalClockParallel LogicExpanders(from other MCs)7000 has two Global ClockProgrammableRegisterRegisterBypassPRnQto I/OControlBlockProduct-TermSelectMatrixDENAVCCCLRnClearSelectClock/EnableSelectShared LogicExpandersto PIA36 ProgrammableInterconnectSignals16 ExpanderProduct Terms
7 MAX II: The Lowest-Cost CPLD Ever New Logic Architecture1/2 the Cost1/10 the Power Consumption2X the Performance4X the DensityNon-Volatile, Instant-OnSupports 3.3-, 2.5- & 1.8-V Supply VoltagesThe four key benefits are compared to MAX: ½ cost; 1/10 power; 2X performance; 4X density.Non-volatility, instant-on, single-chip are “must have” characteristics of a CPLD.Flexible supply voltage details – 3.3V & 2.5V are a single ordering code; 1.8V is a separate ordering code (separate mask set). 1.8V option will be same price, same performance, with lower power.Breakthrough Technologyto Expand the Market
8 Flexible Supply Voltage On-Chip Voltage RegulatorAccepts 3.3-, 2.5- & 1.8-V Supply InputsInternally Converted to 1.8-V Core Voltage2.5 V3.3 V1.8 VTwo sets of ordering codes, e.g. EPM1270 (2.5V/3.3V) and EPM1270G (1.8V). Performance and price are the same. Power is much lower in the 1.8V version (2mA standby vs. 12mA standby) because it bypasses the regulator.3.3/2.5V version will be available first. 1.8V version will follow at a later time.Did not make 1 single device with all 3 Vcc options because we wanted to have a low power device (1.8V). This bypasses the voltage regulator so it doesn’t draw the current associated with that regulator.Convenience of 3.3 V with the Power & Performance of 1.8 V
9 MAX II Device Family Device Logic Elements (LEs) Typical Macro-cells User I/O PinsSpeed GradesFastest tpd1 (ns)User Flash Memory(bits)EPM240240192803, 4, 54.78,192EPM5705704401605.5EPM12701,2709802126.3EPM22102,2101,7002727.1Densities lower than 128 MCs addressed with current MAX device families. They still meet the fitting, performance and I/O requirements of current designs.Typical macrocells are shown to give an approximate density for designers who are accustomed to thinking in macrocells. These are not absolute conversions, but are based on a 1.3 logic element to 1 macrocell ratio, based on a suite of benchmark designs.The speed grades are FPGA-like and do NOT represent absolute tpd. -3 is the fastest, -4 is medium and -5 is slowest. Each density has a different spec for each speed grade.
10 MAX II Packaging & User I/O Pins Device100-Pin TQFP1 0.5-mm Pitch 16 x 16 mm144-Pin TQFP 0.5-mm Pitch 22 x 22 mm256-Pin FBGA2 1.0-mm Pitch 17 x 17 mm324-Pin FBGA 1.0-mm Pitch 19 x 19 mmEPM24080EPM57076116160EPM1270212EPM2210204272MAX II is offered in four low-cost packages. These are NOT pin-compatible with MAX CPLDs.Each package was optimized for one specific density to have the max number of I/Os for that package. The EPM570 in the F256 was not the density optimized for that package, which is why it only has 160 I/O.As you increase in density in the same package, you lose I/O to extra GND and VCC pins. The exception is the EPM1270 in the T144 package, which has enough GND and VCC pins, so it doesn’t “lose” any from the EPM570 in the same package.Denotes Vertical MigrationNotes:1. TQFP: thin quad flat pack2. FineLine BGA® package (1.0-mm pitch)
11 New Small Packages Packages minimize PCB area and optimize ease-of-use 1.0mm FBGA17x17mmT1000.5mm TQFP16x16mmNew PackagesPartialM1000.5mm MBGA6x6mmPartialM2560.5mm MBGA11x11mmPackages minimize PCB area and optimize ease-of-usePartial arrays allow for 2 layer PCB break out
12 MAX II Architecture Logic Elements (LEs) Staggered I/O Pads The MAX II floorplan consists of a staggered ring of I/O, which are optimized for small size & pad pitch. This “donut” ring of I/Os defines the actual die size. Inside the I/O ring, we used SRAM-based, logic elements (4-input LUT plus register) to achieve the highest logic efficiency at the lowest price points. The configuration flash memory block and user flash memory block are the non-volatile part of the device. The configuration flash memory loads the design into the SRAM core upon power up, and the user flash memory (8Kb) can be used to store user data. The user does not have access to the config flash memory block. The config flash memory block size ranges from Kb, depending on device density.This depiction is a marketing diagram – the actual floorplan shape is shown in the datasheet & in the software.Configuration Flash MemoryJTAG & Control CircuitryUser Flash Memory
13 MAX II Logic Element (LE) sloadsclearaloadRegister ChainaddnsubRegRow, Column & Direct Link Routing4-InputLUTdata1data2clock ena aclrdata3Local RoutingcinIdentical to Cyclone devicesEnhanced register packing due to combination of LUT & register chainRegister can be used on LE input, not just outputRegister feedback is useful when you want to register the input of a block in a block-based designIt saves you from having to consume an entire LE to implement an input registerThe combination of the register chain and feedback reduces LE resource usage on average by about 20% versus APEX IIdata4LUT ChainRegister Chain
14 User Flash Memory Block FeatureFlash Memory Storage Bank8,192 Bits Per DeviceInterface to SPI, I2C, Parallel, or Proprietary BusesApplicationsStore Revision & Serial Number DataStore Boot-Up & Configuration DataIndustryFirst!Every device has the same number of user flash memory bits, 8192.Current program/erase spec is for 100 cycles.Serial EEPROM manufactures – ST, Philips, Atmel, Dallas-Maxim usually have different interfaces like SPI, I2C, serial or parallelManufacturing Data – Date, serial number, test information, firmware, board IDSystem Parameters – interrupt address map, IP or port address, Laser or Motor bias current, analogue offsetsUser Parameters – radio channel or telephone number presetsUser Flash Memory Block
15 MAX & MAX II Comparison Parameter MAX MAX II Process Technology 0.3-um EEPROM0.18-um FlashLogic ArchitectureProduct TermLook-Up Table (LUT)Density Range32 to 512 Macrocells128 to 2210 Macrocells(240 to 2,210 LEs)Routing ArchitectureGlobalRow & ColumnOn-Chip Flash MemoryNone8 KbitsMaximum User I/O Pins212272Supply Voltage5.0 V, 3.3 V, 2.5 V3.3 V/2.5 V, 1.8 VI/O Voltages5.0 V, 3.3 V, 2.5 V, 1.8 V3.3 V, 2.5 V, 1.8 V, 1.5 VGlobal Clock Networks2 per Device4 per DeviceOutput Enables (OEs)6 to 10 per Device1 per I/O PinSchmitt Triggers
16 What is Nios II?Altera’s Second Generation Soft-Core 32 Bit RISC MicroprocessorDeveloped Internally By AlteraHarvard ArchitectureRoyalty-Free- Nios II Plus All Peripherals Written In HDL- Can Be Targeted For All Altera FPGAs- Synthesis Using Quartus II Integrated SynthesisAvalon Switch FabricUARTGPIOTimerSPISDRAMControllerOn-ChipROMRAMNios IICPUDebugCacheFPGANios II is a soft-core 32 bit RISC microprocessor that has been developed internally by Altera. It’s based on a Harvard architecture with a 32-bit instruction and data path, separate instruction and data cache, and 32 general purpose registers, and three formats of triadic instructions. It’s closely related to the public domain Stanford MIPS. It’s similar to Nios but is higher performance, has an improved software development flow using the new Nios II IDE (which will be discussed as the presentation rolls along), and it now comes in three “flavors” which I will also discuss shortly.So what does it mean to say “soft-core” processor?It means that the processor, itself, if synthesized out of the logic elements of the particular device architecture that you are programming your part into. In other words, the up is buried in the FPGA.This differs significantly from the common notion of what embedded processors are (ie. off the shelf discrete up’s that you can purchase and implement on a board), and it also differs significantly from a custom ASSP-type hard-core processor which is really a dedicated region of silicon where a processor core gets pre-fabricated into the FPGA. That region of the FPGA will always have the same function on your chip (ie. to be a microprocessor).The soft-core processor is constructed from general purpose gates, routing resources, etc. and offers tremendous flexibility advantages over the more conventional microprocessors, and we’ll get into why this is so as we move along.NBConfigurable Soft-Core ProcessorWorld’s most versatile processor
17 Nios II Processor Architecture Classic Pipelined RISC Machine32 General Purpose Registers3 Instruction Formats32-Bit Instructions32-Bit Data PathFlat Register FileSeparate Instruction and Data Cache (configurable sizes)Tightly-Coupled Memory OptionsBranch Prediction32 Prioritized InterruptsOn-Chip Hardware (Multiply, Shift, Rotate)Custom InstructionsJTAG-Based Hardware Debug Unit<go through these comparisons for those that are familiar with Nios>
18 Problem: Reduce Cost, Complexity & Power CPUI/OFlashSDRAMI/OFPGAFPGADSPI/OI/OI/OI/OWhy is Nios so attractive?Traditional approach – board level integration using discrete componentsCPUDSPSolution: Replace External Devices with Programmable Logic
19 Problem: Reduce Cost, Complexity & Power System On A Programmable Chip (SOPC)Problem: Reduce Cost, Complexity & PowerFPGAFlashSDRAMWhy is Nios so attractive?Traditional approach – board level integration using discrete componentsCPU is a Critical Control Function Required for System-Level IntegrationSolution: Replace External Devices with Programmable Logic
20 Licensing Nios II Delivered As Encrypted Megacore Licensed Via Feature Line In Existing Quartus II License FileConsistent With General Altera Megacore Delivery MechanismEnables Detection Of Nios II In Customer Designs (Talkback)No Nios II Feature Line (OpenCore Plus Mode)System Runs If Tethered To Host PCSystem Times Out If Disconnected from PC After ~ 1 hrNios II Feature Line (Active Subscriber)Subscription and New Dev Kit Customers Obtain Licenses FromNios II CPU RTL Remains EncryptedNios II Source LicenseAvailable Upon Request On Case-By-Case BasisIncluded With Purchase Of Nios II ASIC LicenseNios II ships as an encrypted megacore, just like all other megacore IP from Altera. There are three ways to use Nios II depending on the license:1. No Nios II License File Feature Line . Nios II will generate FPGA configuration files that operate in OpenCore Plus mode. In other words, as long as the customer.s board is tethered to the host PC (Quartus II), the Nios II system will run. After they disconnect from the host PC (~ 1 hour), the design will timeout and stop running. OpenCore Plus lets customers design, simulate and run Nios II based designs without having to purchase a development kit.2. Nios II License File Feature Line (Active Subscriber) . Customers who purchase a Nios II development kit, or who receive a Nios II upgrade (i.e. all active Nios subscribers as of May, 2004), must request a Nios II license from the Altera web site which will add a FlexLM feature line to their Altera license file which will enable them to generation configuration files that have no time limit. The RTL generated for the Nios II CPU core is encrypted.Nios II Source License . Customers who purchase a Nios II ASIC license will get an additional feature line to enable plain text RTL generation of the Nios II processor core. If you have a customer who absolutely insists on getting full source code, it can be made available on a case-by-case basis.--Note: Nios II IDE does not require a license. Thus, you do not require a license to develop code for use with Nios II. Also, you can sort out a license server arrangement for Quartus II and Nios II.
21 Quartus II Basic Training Quartus II Development SystemFeature Overview
22 Software & Development Tools Quartus IIAll Stratix, Cyclone & Hardcopy DevicesAPEX II, APEX 20K/E/C, Excalibur, & Mercury DevicesFLEX 10K/A/E, ACEX 1K, FLEX 6000 DevicesMAX II, MAX 7000S/AE/B, MAX 3000A DevicesQuartus II Web EditionFree VersionNot All Features & Devices IncludedSee for Feature ComparisonMAX+PLUS® IIAll FLEX, ACEX, & MAX Devices
23 Quartus II Development System Fully-Integrated Design ToolMultiple Design Entry MethodsLogic SynthesisPlace & RouteSimulationTiming & Power AnalysisDevice Programming
24 Typical PLD Design Flow Design SpecificationDesign Entry/RTL Coding- Behavioral or Structural Description of DesignRTL Simulation- Functional Simulation (Modelsim®, Quartus II)- Verify Logic Model & Data Flow(No Timing Delays)M512Synthesis- Translate Design into Device Specific Primitives- Optimization to Meet Required Area & Performance Constraints- Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA, Quartus IILEM4KI/OPlace & Route- Map Primitives to Specific Locations insideTarget Technology with Reference to Area &Performance Constraints- Specify Routing Resources to Be Used
25 Typical PLD Design Flow tclkTiming Analysis- Verify Performance Specifications Were Met- Static Timing AnalysisGate Level Simulation- Timing Simulation- Verify Design Will Work in Target TechnologyPC Board Simulation & Test- Simulate Board Design- Program & Test Device on Board- Use SignalTap II for Debugging
26 Imported from 3rd-Party EDA tools Design Entry MethodsQuartus IIText EditorAHDLVHDLVerilogSchematic EditorBlock Diagram FileGraphic Design FileMemory EditorHEXMIF3rd-Party EDA ToolsEDIFHDLVQMMixing & Matching Design Files AllowedTop-level design files can be schematic, HDL or 3rd-Party Netlist FileBlockFileSymbolTextImported from 3rd-Party EDA toolsGenerated within Quartus II.v, vlg,.vhd, .vhdl, vqm.edf.edif.v.vhd.tdf.bsf.bdf.gdfTop-Level File
27 Quartus II Basic Training Quartus II Quick Start LAB1
28 Objectives Create a project using the New Project Wizard Name the projectAdd design filesPick a device
29 Step 1 (Setup Project for QII5_1) Under File, Select New Project Wizard….A new window appears. If an Introductionscreen appears, click Next.
30 Step 2 (Setup Project for QII5_1) Page 1 of the wizard should be completed with the followingworking directory for this project<lab_install_directory> \Dsp_7_segment\name of projectDsp_7_segmenttop-level design entityCopy “state_machine.v” and past inDsp_7_segmentClick Next to advance to theProject Wizard: Add Files [page 2 of 5].
31 Step 3 (Setup Project for QII5_1) Using the browse button, select state_machine.vAdd to the project. Click Next.
32 Step 4 (Setup Project for QII5_1) On page 3, select Stratix as the Family. Also, in the Filters section,set Package to FBFA, Pin count to 780, and Speed grade to 5.Select the EP1S25F780C5 device fromthe Available devices: window. Click Next.
33 Step 5 (Setup Project for QII5_1) On page 4 , you can specify any third party EDA tools you may be usingalong with Quartus II. Since these exercises will be done entirely withinQuartus II, click Next.
34 Step 6 (Setup Project for QII5_1) The summary screen appears as shown. Click Finish.The project is now created.
35 Quartus II Basic Training Quartus II Quick Start LAB2
36 Objectives Create a counter using the MegaWizard Plug-in Manager Build a design using the schematic editorAnalyze and elaborate the design to check for errors
37 Step 1 Create schematic file Select File New and select Block Diagram/Schematic File. Click OK.Select File Save As and save the file as<lab_install_directory> \Dsp_7_segment\ Dsp_7_segment.bdf
38 Step 2 Build an 23 bits counter using the MegaWizard Plug-in Manager 1.Choose Tools MegaWizard Plug-In Manager. In the window that appears, select Create a new custom megafunction variation. Click on Next.2.On page 2a of the MegaWizard expand the arithmetic folder and select LPM_COUNTER.3.Choose Verilog HDL output For the name of the output file, type timer_1s.Click on Next
39 Step 3Set the output bus to 27 bits. For the remaining settings in this window, use the defaults that appear .. Select next.Turn on “Modulus , with a count modulus of “and key inSelect finish
40 Step 4In the Graphic Editor, double-click in the screen so that the Symbol Windowappears. Inside the symbol window, click on to expand the symbols definedin the Project folder. Double-click on timer_1s. Click theleft mouse button to put down the symbol inside the schematic file.. The symbolfor “timer_1s” now appears in the schematic.
41 Step 5 From the File menu, open the file state_machine.v From the File menu, go the Create/Update menu option and select Create Symbol Files for Current File. Click Yes to save changes to Dsp_7_segment.bdf.Once Quartus II is finished creating the symbol, click OK. Close the state_machine.v fileIn the Graphic Editor, double-click in the screen so that the Symbol Window appears again. Double-click on state_machine in the Project folder. Click OK... The symbol for state_machine now appears in the schematic.
42 Step 6 Add Pins to the Design InputOutputsys_clk7_out[6..0]resetDig1For each of the pins listed in left Table , you must insert a pin and change its nameTo place pins in the schematic file, go to Edit Insert Symbol OR double-click in any empty location of the Graphic Editor.Browse to libraries primitives pin folder. Double-click on input or output Hint: To insert multiple pins select Repeat Insert Mode.To rename the pins double-click on the pin name after it has been inserted.Type the name in the Pin name(s) field and Click OK.
43 Step 7 Connect the Pins and Blocks in the Schematic In the left hand tool bar click on button to draw a wire and button to draw a bus. Another way to draw wires and busses is to place the cursor next to the port of any symbol. When you do this, the wire or bus tool will automatically appear.Connect all of the pins and blocks as shown in the figure below
44 Step 8 Save and check the schematic Click on the Save button in the toolbar to save the schematic.From the Project menu, select Add/Remove Files in Project. Click on the browse button to make sure the Dsp_7_segment.bdf, timer_1s and state_machine are added to the project.From the Processing menu, select Start Start Analysis & Elaboration. Analysis and elaboration checks that all the design files are present and connections have been made correctly.Click OK when analysis and elaboration is completed
45 Quartus II Basic Training Quartus II Quick Start LAB3
46 Objectives Pin assignment Perform full compilation Build a design using the schematic editorHow to Download programming file
47 Step 1 Choose Assignments Assignment editor. From the View menu, select Show All Know Pin Names.Please click Pin in Category
48 Step 2 Pls install DSP Development Kit Stratix edtion CD Open ds_stratix_dsp_bd.pdf from C:\megacore\stratix_dsp_kit-v1.1.0\DocCheck clk , pushbotton and seven segment display pin location from ds_stratix_dsp_bd.pdfKey your pin number in locationClick on the Save button in the toolbarFrom Assignments, select Device. Click Device & Pin options. Click Unused pins .Select As input tri-stated from Reserve all unused pinsFrom the Processing menu, select Start Compilation
49 Step 3 From the Tools menu, select programmer Click on Add File. Select Dsp_7_segment.sof.Check Hardware Setup. Select your download cable on Currently selected hardware(ByteBlasterII)Select JTAG from Mode
50 Step 4 Turn on Program/configure. Or see figure below Click Start See 7-segment status
51 SignalTap II Agenda SignalTap II Overview & Features Using SignalTap II InterfaceAdvanced Triggering
52 SignalTap II ELACaptures the Logic State of FPGA Internal Signals Using a Defined Clock SignalGives Designers Ability to Monitor Buried SignalsConnects to Quartus II through FPGA JTAG PinsCaptures Real-Time DataUp to 200 MhzIs Available for FreeInstalled with Full Subscription or Web EditionInstalled with Stand-Alone Programmer
53 SignalTap II Device Support Stratix & Stratix IIStratix GXCyclone & Cyclone IIExcaliburMercuryAPEX IIAPEX 20K/E/C
54 How Does It Work? Configure ELA Download ELA into FPGA along with DesignELA Samples Internal SignalsQuartus II Communicates with ELA through JTAG
55 Stratix/Cyclone Sample Resource Usage Number of ChannelsLogic ElementsTrigger Level 1Trigger Level 2Trigger Level 3831637142632566773981256290045286156Number of ChannelsM4Ks Based on Sample Depth2565122K8K32K8< 1141664322128
56 Modes of Operation Three Different Configurations Internal RAM ELA ConfigurationDebug Port ELA ConfigurationHybrid ApproachProvides Flexibility Based on Available Device ResourcesMemory Resources Are LimitedUse Debug Port ConfigurationPin Resources Are LimitedUse Internal RAM Configuration
57 Supported Download Cables USB BlasterUSB Port CableByteBlaster™ IIParallel Port CableByteBlasterMV™Parallel PortMasterBlaster™USB / Serial Port Cable
58 SignalTap II Key Features SetupData TriggeringData CaptureData Analysis
59 Setup Features Up to 1024 Data Channels Data TriggeringData CaptureData AnalysisUp to 1024 Data ChannelsMultiple Analyzers in One DeviceSupports Analysis of Multiple Clock DomainsEach Analyzer Can Run SimultaneouslyResource Usage EstimationIncremental Design Support
60 Data Triggering Features SetupData TriggeringData CaptureData AnalysisUp to 10 Trigger Levels Per ChannelAllows Application of Simple (Basic) & Complex (Advanced) Triggering SchemesDefines a Sequential Pattern of Logic ConditionsEach Trigger Level is Logically ANDEDIf (L1 & L2 ... & L10) == TRUE Data Capture
61 Data Triggering Features (Cont.) SetupData TriggeringData CaptureData AnalysisThree Main Trigger PositionsTrigger InputSetup External Trigger to Trigger the AnalyzerTrigger OutputSignifies Trigger Event Occurred with SignalTap IIUse One ELA’s Trigger Output as Trigger Input for AnotherTIMEOld SamplesNew SamplestriggerSamples CapturedData Triggering
62 Data Capture Features Up to 128K Samples Per Channel SetupData TriggeringData CaptureData AnalysisUp to 128K Samples Per ChannelIncreases Chance of Catching Target EventTwo Methods of Data AcquisitionCircularSegmentedMnemonic TablesCreate User-Defined Labels for Bit Sequences (Ex. State Machine)
63 SignalTap II Design Flow Use SignalTap II File (.STP)Use Quartus II GUISTP Separate from Design FilesUse Quartus II MegaWizardInstantiate Directly into HDL
64 Using STP File Create .STP File Save .STP File & Compile with Design Assign Sample ClockSpecify Sample DepthAssign Signals to STP FileSpecify TriggeringSetup JTAGSave .STP File & Compile with DesignProgram DeviceAcquire Data
65 1) Creating a New .STP File To Create a .STP FileMethod 1Select the in Quartus IIMethod 2Select New (File Menu)Other FilesSignalTap II FileDefault File Name Will Be STP1.stp
67 Instance Manager Instance Manager Selects Current ELA to Setup/View Displays the Current Status of each InstanceDisplays Size (Resource Usage) of ELA
68 Assign Sample Clock Use Global Clock for Best Results Data Written to Memory on Every Sample Clock Rising EdgeClock Signal Cannot Be Monitored as DataExternal Clock Pin Created Automatically if Clock Unassignedauto_stp_external_clockELA Expects External Signal to be Connected to Clock Pin
69 Specify Sample Depth Sample Depth Set Number of Samples Stored for each Data Signal0 to 128K Sample Depth0 Selected When External Analyzer Is UsedSelect RAM Type for Stratix & Stratix II DevicesUseful when Preserving a Specific Memory Type is Necessary
70 Data Capture Circular Segmented Specify Trigger Position PreCenterPostContinuousSegmentedSpecify Segment Depth
71 Triggering Trigger Levels Trigger-In Trigger-Out Indicate up to 10 Trigger ConditionsTrigger-InAny I/O Pin Can Trigger the SignalTap II AnalyzerGenerates auto_stp_trigger_in_n PinTrigger-OutIndicates When a Trigger Pattern OccursGenerates auto_stp_trigger_out_n PinDelayed 4 Clock Cycles after Actual Trigger Event
72 Waveform Viewer Setup Tab Describes the Signal Settings Data Signals vs. Trigger SignalsSets up Each Triggering Level (L1 – L10)Data Tab Displays Captured Data
74 Basic TriggeringAll Signals Must Be True for Level to Cause Data CaptureRight-Click to Set Value
75 Debug PortRoutes Data Signals to Spare I/O Pins for Capture by External Logic AnalyzerQuartus II Automatically Generates auto_stp_debug_out_m_n Pinm Represents the Instance Number of the Analyzern Represents the Order the Debug Port Pin Occurs in the Signal List
76 Mnemonic TableAllows a Set of Bit Patterns to Be Assigned User-Defined NamesRight-Click in the Setup View of an STP File & Select Mnemonic SetupSelect Add TableSelect Add EntryEx. State Machines or Decoders/Encoders
77 JTAG Chain Configuration Select Programming HardwareScan Chan Button Automatically Determines Devices Physically Connected to the ChainDetects Non-Altera Devices & Displays Them as Unknown
78 2) Save .STP File & Compile SignalTap II Logic Analyzer Control in Compiler SettingsAssignments SettingsSpecify the STP File to Compile with Project
79 3) Program Device(s) Use Quartus II Programmer or STP File Program Button in the SignalTap II Interface Only Configures the Selected Device in ChainUse Quartus II Programmer to Program Multiple DevicesCan Create a STP File for each Device in the JTAG Chain
80 4) Acquire Data SignalTap II Toolbar & STP File Controls Run Autorun StopRead Data (Reads in Data from Last Analysis)
81 Displaying Acquired Data Format in Time or Sample NumberDisplay Signal as Bar or Line ChartExport to Other Tools for Viewing or Analysis (File Menu)Creates .VWF, .TBL, .CSV, .VCD, .JPG or .BMP File
82 Using STP File Review Create .STP File Assign Sample ClockSpecify Sample DepthAssign Signals to STP FileSpecify TriggeringSetup JTAGSave .STP File & Compile with DesignProgram DeviceAcquire Data
83 Recompilation Recompilation Required Addition/Removal of Instance, Data or TriggerModifying the Sample Clock or Buffer DepthEnabling/Modifying Trigger-In/Trigger-OutEnabling the Debug PortLock Mode Prevents Changes Requiring Recompilation
84 Reducing Recompilation Times Incremental CompilationMaintains Design Synthesis & PlacementRecompiles Only Logic AnalyzerChange SignalTap II Configuration without Affecting Existing LogicIncremental RoutingAllows Switching Trigger & Data Nodes without Full RecompilationCannot Be Used Together in 5.0Use Incremental Compilation First, Switch to RoutingWill Be Supported in Future Version of Quartus II
85 SignalTap II Incremental Compilation Enable Full Incremental CompilationAny User-DefinedPartitions Must BeRemoved(5.0 Limitation)Set Netlist Type of Top-Level Partition to Post-FitAssignments Menu
86 SignalTap II Incremental Compilation Compile DesignEnable SignalTap II Incremental CompilationOnly Post Fitting Nodes Can Be Incrementally CompiledQuartus II Will Automatically Convert Pre-Synthesis Nodes to Post-Fitting
87 SignalTap II Incremental Routing Enable Smart RecompilationManually Set the Number of Allocated NodesNodes Acts as Place Holders for Real Signals that Can Be Added LaterAuto Creates Enough Nodes for Current Number of Data/Triggers
88 SignalTap II Incremental Routing Add Post-Fitting nodes to STP fileSignalTap II: Post-Fitting Nodes Always Incrementally RoutedSignalTap II: Pre-Synthesis Nodes Always Cause Full Recompilation if Added LaterBenefit of Enabling Incremental Routing on Pre-Synthesis Nodes is They Can Be Removed & Replaced with Post-fitting Nodes without Total RecompilationPre-Synthesis NodesPost-fitting Nodes
89 Quartus II Netlist Optimization New Synthesis Optimization Features Do Not Work Well with SignalTap IISignalTap II Nodes may DisappearRegister Re-timing & WYSIWYG Re-Synthesis Should be Disabled if SignalTap II is UsedSet Netlist Optimizations Logic Option to Never Allow on Entities which Have SignalTap II Nodes
90 Performance Preservation SignalTap II can Potentially Effect the Performance of a DesignRouting and/or Placement Can ChangePossible SolutionBack-Annotate Design before Adding SignalTap IISee Quartus II Handbook, Volume 3, Chapter 10 for More Suggestions