Quartus II Basic Training

Quartus II Basic Training

Programmable Logic Families
Structured ASIC HardCopy® II, HardCopy Stratix High & Medium Density FPGAs Stratix II, Stratix, APEX™ II, APEX 20K, & FLEX 10K® Low-Cost FPGAs Cyclone II & Cyclone FPGAs with Clock Data Recovery Stratix II GX CPLDs MAX II, MAX 7000 & MAX 3000 Embedded Processor Solutions Nios II Configuration Devices Serial (EPCS) & Enhanced (EPC)

MAX 7000A & MAX 3000A Family Overview
Parameter MAX 3000A MAX 7000A EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A EPM7032AE EPM7064AE EPM7128AE EPM7256AE EPM7512AE Useable Gates Macrocells Maximum User I/O Pins tPD (ns) fCNT (MHz) tSU (ns) tCO1 (ns) 600 32 34 4.5 227 2.9 3.0 1,250 64 66 4.5 222 2.8 3.1 2,500 128 96 5.0 192 3.3 3.4 5,000 256 158 7.5 127 5.2 4.8 10,000 512 208 7.5 116 5.6 4.7 600 32 36 4.5 227 2.9 3.0 1,250 64 68 4.5 222 2.8 3.1 2,500 128 100 5.0 192 3.3 3.4 5,000 256 164 5.5 172 3.9 3.5 10,000 512 212 7.5 116 5.6 4.7

Complete Voltage Portfolio
MAX 7000S MAX 7000AE MAX 7000B Performance Leader Feature Leader Wide Range of Package Offerings Industrial-Grade Offerings High Performance Feature Leader Wide Range of Package Offerings High Performance Feature Leader Wide Range of Package Offerings MAX 3000A Price Leader Feature & Package Subset of MAX 7000AE

MAX Device Block Diagram

MAX Macrocell Parallel Logic Expanders (from other MCs) Programmable
Global Clear Global Clock Parallel Logic Expanders (from other MCs) 7000 has two Global Clock Programmable Register Register Bypass PRn Q to I/O Control Block Product- Term Select Matrix D ENA VCC CLRn Clear Select Clock/ Enable Select Shared Logic Expanders to PIA 36 Programmable Interconnect Signals 16 Expander Product Terms

MAX II: The Lowest-Cost CPLD Ever
New Logic Architecture 1/2 the Cost 1/10 the Power Consumption 2X the Performance 4X the Density Non-Volatile, Instant-On Supports 3.3-, 2.5- & 1.8-V Supply Voltages The four key benefits are compared to MAX: ½ cost; 1/10 power; 2X performance; 4X density. Non-volatility, instant-on, single-chip are “must have” characteristics of a CPLD. Flexible supply voltage details – 3.3V & 2.5V are a single ordering code; 1.8V is a separate ordering code (separate mask set). 1.8V option will be same price, same performance, with lower power. Breakthrough Technology to Expand the Market

Flexible Supply Voltage
On-Chip Voltage Regulator Accepts 3.3-, 2.5- & 1.8-V Supply Inputs Internally Converted to 1.8-V Core Voltage 2.5 V 3.3 V 1.8 V Two sets of ordering codes, e.g. EPM1270 (2.5V/3.3V) and EPM1270G (1.8V). Performance and price are the same. Power is much lower in the 1.8V version (2mA standby vs. 12mA standby) because it bypasses the regulator. 3.3/2.5V version will be available first. 1.8V version will follow at a later time. Did not make 1 single device with all 3 Vcc options because we wanted to have a low power device (1.8V). This bypasses the voltage regulator so it doesn’t draw the current associated with that regulator. Convenience of 3.3 V with the Power & Performance of 1.8 V

MAX II Device Family Device Logic Elements (LEs) Typical Macro-cells
User I/O Pins Speed Grades Fastest tpd1 (ns) User Flash Memory (bits) EPM240 240 192 80 3, 4, 5 4.7 8,192 EPM570 570 440 160 5.5 EPM1270 1,270 980 212 6.3 EPM2210 2,210 1,700 272 7.1 Densities lower than 128 MCs addressed with current MAX device families. They still meet the fitting, performance and I/O requirements of current designs. Typical macrocells are shown to give an approximate density for designers who are accustomed to thinking in macrocells. These are not absolute conversions, but are based on a 1.3 logic element to 1 macrocell ratio, based on a suite of benchmark designs. The speed grades are FPGA-like and do NOT represent absolute tpd. -3 is the fastest, -4 is medium and -5 is slowest. Each density has a different spec for each speed grade.

MAX II Packaging & User I/O Pins
Device 100-Pin TQFP1 0.5-mm Pitch 16 x 16 mm 144-Pin TQFP 0.5-mm Pitch 22 x 22 mm 256-Pin FBGA2 1.0-mm Pitch 17 x 17 mm 324-Pin FBGA 1.0-mm Pitch 19 x 19 mm EPM240 80 EPM570 76 116 160 EPM1270 212 EPM2210 204 272 MAX II is offered in four low-cost packages. These are NOT pin-compatible with MAX CPLDs. Each package was optimized for one specific density to have the max number of I/Os for that package. The EPM570 in the F256 was not the density optimized for that package, which is why it only has 160 I/O. As you increase in density in the same package, you lose I/O to extra GND and VCC pins. The exception is the EPM1270 in the T144 package, which has enough GND and VCC pins, so it doesn’t “lose” any from the EPM570 in the same package. Denotes Vertical Migration Notes: 1. TQFP: thin quad flat pack 2. FineLine BGA® package (1.0-mm pitch)

New Small Packages Packages minimize PCB area and optimize ease-of-use
1.0mm FBGA 17x17mm T100 0.5mm TQFP 16x16mm New Packages Partial M100 0.5mm MBGA 6x6mm Partial M256 0.5mm MBGA 11x11mm Packages minimize PCB area and optimize ease-of-use Partial arrays allow for 2 layer PCB break out

MAX II Architecture Logic Elements (LEs) Staggered I/O Pads
The MAX II floorplan consists of a staggered ring of I/O, which are optimized for small size & pad pitch. This “donut” ring of I/Os defines the actual die size. Inside the I/O ring, we used SRAM-based, logic elements (4-input LUT plus register) to achieve the highest logic efficiency at the lowest price points. The configuration flash memory block and user flash memory block are the non-volatile part of the device. The configuration flash memory loads the design into the SRAM core upon power up, and the user flash memory (8Kb) can be used to store user data. The user does not have access to the config flash memory block. The config flash memory block size ranges from Kb, depending on device density. This depiction is a marketing diagram – the actual floorplan shape is shown in the datasheet & in the software. Configuration Flash Memory JTAG & Control Circuitry User Flash Memory

MAX II Logic Element (LE)
sload sclear aload Register Chain addnsub Reg Row, Column & Direct Link Routing 4-Input LUT data1 data2 clock ena aclr data3 Local Routing cin Identical to Cyclone devices Enhanced register packing due to combination of LUT & register chain Register can be used on LE input, not just output Register feedback is useful when you want to register the input of a block in a block-based design It saves you from having to consume an entire LE to implement an input register The combination of the register chain and feedback reduces LE resource usage on average by about 20% versus APEX II data4 LUT Chain Register Chain

User Flash Memory Block
Feature Flash Memory Storage Bank 8,192 Bits Per Device Interface to SPI, I2C, Parallel, or Proprietary Buses Applications Store Revision & Serial Number Data Store Boot-Up & Configuration Data Industry First! Every device has the same number of user flash memory bits, 8192. Current program/erase spec is for 100 cycles. Serial EEPROM manufactures – ST, Philips, Atmel, Dallas-Maxim usually have different interfaces like SPI, I2C, serial or parallel Manufacturing Data – Date, serial number, test information, firmware, board ID System Parameters – interrupt address map, IP or port address, Laser or Motor bias current, analogue offsets User Parameters – radio channel or telephone number presets User Flash Memory Block

MAX & MAX II Comparison Parameter MAX MAX II Process Technology
0.3-um EEPROM 0.18-um Flash Logic Architecture Product Term Look-Up Table (LUT) Density Range 32 to 512 Macrocells 128 to 2210 Macrocells (240 to 2,210 LEs) Routing Architecture Global Row & Column On-Chip Flash Memory None 8 Kbits Maximum User I/O Pins 212 272 Supply Voltage 5.0 V, 3.3 V, 2.5 V 3.3 V/2.5 V, 1.8 V I/O Voltages 5.0 V, 3.3 V, 2.5 V, 1.8 V 3.3 V, 2.5 V, 1.8 V, 1.5 V Global Clock Networks 2 per Device 4 per Device Output Enables (OEs) 6 to 10 per Device 1 per I/O Pin Schmitt Triggers

What is Nios II? Altera’s Second Generation Soft-Core 32 Bit RISC Microprocessor Developed Internally By Altera Harvard Architecture Royalty-Free - Nios II Plus All Peripherals Written In HDL - Can Be Targeted For All Altera FPGAs - Synthesis Using Quartus II Integrated Synthesis Avalon Switch Fabric UART GPIO Timer SPI SDRAM Controller On-Chip ROM RAM Nios II CPU Debug Cache FPGA Nios II is a soft-core 32 bit RISC microprocessor that has been developed internally by Altera. It’s based on a Harvard architecture with a 32-bit instruction and data path, separate instruction and data cache, and 32 general purpose registers, and three formats of triadic instructions. It’s closely related to the public domain Stanford MIPS. It’s similar to Nios but is higher performance, has an improved software development flow using the new Nios II IDE (which will be discussed as the presentation rolls along), and it now comes in three “flavors” which I will also discuss shortly. So what does it mean to say “soft-core” processor? It means that the processor, itself, if synthesized out of the logic elements of the particular device architecture that you are programming your part into. In other words, the up is buried in the FPGA. This differs significantly from the common notion of what embedded processors are (ie. off the shelf discrete up’s that you can purchase and implement on a board), and it also differs significantly from a custom ASSP-type hard-core processor which is really a dedicated region of silicon where a processor core gets pre-fabricated into the FPGA. That region of the FPGA will always have the same function on your chip (ie. to be a microprocessor). The soft-core processor is constructed from general purpose gates, routing resources, etc. and offers tremendous flexibility advantages over the more conventional microprocessors, and we’ll get into why this is so as we move along. NB Configurable Soft-Core Processor World’s most versatile processor

Nios II Processor Architecture
Classic Pipelined RISC Machine 32 General Purpose Registers 3 Instruction Formats 32-Bit Instructions 32-Bit Data Path Flat Register File Separate Instruction and Data Cache (configurable sizes) Tightly-Coupled Memory Options Branch Prediction 32 Prioritized Interrupts On-Chip Hardware (Multiply, Shift, Rotate) Custom Instructions JTAG-Based Hardware Debug Unit <go through these comparisons for those that are familiar with Nios>

Problem: Reduce Cost, Complexity & Power
CPU I/O Flash SDRAM I/O FPGA FPGA DSP I/O I/O I/O I/O Why is Nios so attractive? Traditional approach – board level integration using discrete components CPU DSP Solution: Replace External Devices with Programmable Logic

Problem: Reduce Cost, Complexity & Power
System On A Programmable Chip (SOPC) Problem: Reduce Cost, Complexity & Power FPGA Flash SDRAM Why is Nios so attractive? Traditional approach – board level integration using discrete components CPU is a Critical Control Function Required for System-Level Integration Solution: Replace External Devices with Programmable Logic

Licensing Nios II Delivered As Encrypted Megacore
Licensed Via Feature Line In Existing Quartus II License File Consistent With General Altera Megacore Delivery Mechanism Enables Detection Of Nios II In Customer Designs (Talkback) No Nios II Feature Line (OpenCore Plus Mode) System Runs If Tethered To Host PC System Times Out If Disconnected from PC After ~ 1 hr Nios II Feature Line (Active Subscriber) Subscription and New Dev Kit Customers Obtain Licenses From Nios II CPU RTL Remains Encrypted Nios II Source License Available Upon Request On Case-By-Case Basis Included With Purchase Of Nios II ASIC License Nios II ships as an encrypted megacore, just like all other megacore IP from Altera. There are three ways to use Nios II depending on the license: 1. No Nios II License File Feature Line . Nios II will generate FPGA configuration files that operate in OpenCore Plus mode. In other words, as long as the customer.s board is tethered to the host PC (Quartus II), the Nios II system will run. After they disconnect from the host PC (~ 1 hour), the design will timeout and stop running. OpenCore Plus lets customers design, simulate and run Nios II based designs without having to purchase a development kit. 2. Nios II License File Feature Line (Active Subscriber) . Customers who purchase a Nios II development kit, or who receive a Nios II upgrade (i.e. all active Nios subscribers as of May, 2004), must request a Nios II license from the Altera web site which will add a FlexLM feature line to their Altera license file which will enable them to generation configuration files that have no time limit. The RTL generated for the Nios II CPU core is encrypted. Nios II Source License . Customers who purchase a Nios II ASIC license will get an additional feature line to enable plain text RTL generation of the Nios II processor core. If you have a customer who absolutely insists on getting full source code, it can be made available on a case-by-case basis. -- Note: Nios II IDE does not require a license. Thus, you do not require a license to develop code for use with Nios II. Also, you can sort out a license server arrangement for Quartus II and Nios II.

Quartus II Basic Training
Quartus II Development System Feature Overview

Software & Development Tools
Quartus II All Stratix, Cyclone & Hardcopy Devices APEX II, APEX 20K/E/C, Excalibur, & Mercury Devices FLEX 10K/A/E, ACEX 1K, FLEX 6000 Devices MAX II, MAX 7000S/AE/B, MAX 3000A Devices Quartus II Web Edition Free Version Not All Features & Devices Included See for Feature Comparison MAX+PLUS® II All FLEX, ACEX, & MAX Devices

Quartus II Development System
Fully-Integrated Design Tool Multiple Design Entry Methods Logic Synthesis Place & Route Simulation Timing & Power Analysis Device Programming

Typical PLD Design Flow
Design Specification Design Entry/RTL Coding - Behavioral or Structural Description of Design RTL Simulation - Functional Simulation (Modelsim®, Quartus II) - Verify Logic Model & Data Flow (No Timing Delays) M512 Synthesis - Translate Design into Device Specific Primitives - Optimization to Meet Required Area & Performance Constraints - Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA, Quartus II LE M4K I/O Place & Route - Map Primitives to Specific Locations inside Target Technology with Reference to Area & Performance Constraints - Specify Routing Resources to Be Used

Typical PLD Design Flow
tclk Timing Analysis - Verify Performance Specifications Were Met - Static Timing Analysis Gate Level Simulation - Timing Simulation - Verify Design Will Work in Target Technology PC Board Simulation & Test - Simulate Board Design - Program & Test Device on Board - Use SignalTap II for Debugging

Imported from 3rd-Party EDA tools
Design Entry Methods Quartus II Text Editor AHDL VHDL Verilog Schematic Editor Block Diagram File Graphic Design File Memory Editor HEX MIF 3rd-Party EDA Tools EDIF HDL VQM Mixing & Matching Design Files Allowed Top-level design files can be schematic, HDL or 3rd-Party Netlist File Block File Symbol Text Imported from 3rd-Party EDA tools Generated within Quartus II .v, vlg, .vhd, .vhdl, vqm .edf .edif .v .vhd .tdf .bsf .bdf .gdf Top-Level File

Quartus II Basic Training Quartus II Quick Start LAB1

Objectives Create a project using the New Project Wizard
Name the project Add design files Pick a device

Step 1 (Setup Project for QII5_1)
Under File, Select New Project Wizard…. A new window appears. If an Introduction screen appears, click Next.

Page 1 of the wizard should be completed with the following working directory for this project <lab_install_directory> \Dsp_7_segment\ name of project Dsp_7_segment top-level design entity Copy “state_machine.v” and past in Dsp_7_segment Click Next to advance to the Project Wizard: Add Files [page 2 of 5].

Using the browse button, select state_machine.v Add to the project. Click Next.

On page 3, select Stratix as the Family. Also, in the Filters section, set Package to FBFA, Pin count to 780, and Speed grade to 5. Select the EP1S25F780C5 device from the Available devices: window. Click Next.

On page 4 , you can specify any third party EDA tools you may be using along with Quartus II. Since these exercises will be done entirely within Quartus II, click Next.

The summary screen appears as shown. Click Finish. The project is now created.

Objectives Create a counter using the MegaWizard Plug-in Manager
Build a design using the schematic editor Analyze and elaborate the design to check for errors

Step 1 Create schematic file
Select File  New and select Block Diagram/Schematic File. Click OK. Select File  Save As and save the file as <lab_install_directory> \Dsp_7_segment\ Dsp_7_segment.bdf

Step 2 Build an 23 bits counter using the MegaWizard Plug-in Manager
1.Choose Tools  MegaWizard Plug-In Manager. In the window that appears, select Create a new custom megafunction variation. Click on Next. 2.On page 2a of the MegaWizard expand the arithmetic folder and select LPM_COUNTER. 3.Choose Verilog HDL output For the name of the output file, type timer_1s. Click on Next

Step 3 Set the output bus to 27 bits. For the remaining settings in this window, use the defaults that appear .. Select next .Turn on “Modulus , with a count modulus of “and key in Select finish

Step 4 In the Graphic Editor, double-click in the screen so that the Symbol Window appears. Inside the symbol window, click on to expand the symbols defined in the Project folder. Double-click on timer_1s. Click the left mouse button to put down the symbol inside the schematic file.. The symbol for “timer_1s” now appears in the schematic.

Step 5 From the File menu, open the file state_machine.v
From the File menu, go the Create/Update menu option and select Create Symbol Files for Current File. Click Yes to save changes to Dsp_7_segment.bdf. Once Quartus II is finished creating the symbol, click OK. Close the state_machine.v file In the Graphic Editor, double-click in the screen so that the Symbol Window appears again. Double-click on state_machine in the Project folder. Click OK... The symbol for state_machine now appears in the schematic.

Step 6 Add Pins to the Design
Input Output sys_clk 7_out[6..0] reset Dig1 For each of the pins listed in left Table , you must insert a pin and change its name To place pins in the schematic file, go to Edit  Insert  Symbol OR double-click in any empty location of the Graphic Editor. Browse to libraries  primitives  pin folder. Double-click on input or output Hint: To insert multiple pins select Repeat Insert Mode. To rename the pins double-click on the pin name after it has been inserted. Type the name in the Pin name(s) field and Click OK .

Step 7 Connect the Pins and Blocks in the Schematic
In the left hand tool bar click on button to draw a wire and button to draw a bus. Another way to draw wires and busses is to place the cursor next to the port of any symbol. When you do this, the wire or bus tool will automatically appear. Connect all of the pins and blocks as shown in the figure below

Step 8 Save and check the schematic
Click on the Save button in the toolbar to save the schematic. From the Project menu, select Add/Remove Files in Project. Click on the browse button to make sure the Dsp_7_segment.bdf, timer_1s and state_machine are added to the project. From the Processing menu, select Start  Start Analysis & Elaboration. Analysis and elaboration checks that all the design files are present and connections have been made correctly. Click OK when analysis and elaboration is completed

Objectives Pin assignment
Perform full compilation Build a design using the schematic editor How to Download programming file

Step 1 Choose Assignments  Assignment editor.
From the View menu, select Show All Know Pin Names. Please click Pin in Category

Step 2 Pls install DSP Development Kit Stratix edtion CD
Open ds_stratix_dsp_bd.pdf from C:\megacore\stratix_dsp_kit-v1.1.0\Doc Check clk , pushbotton and seven segment display pin location from ds_stratix_dsp_bd.pdf Key your pin number in location Click on the Save button in the toolbar From Assignments, select Device. Click Device & Pin options. Click Unused pins .Select As input tri-stated from Reserve all unused pins From the Processing menu, select Start Compilation

Step 3 From the Tools menu, select programmer
Click on Add File. Select Dsp_7_segment.sof. Check Hardware Setup. Select your download cable on Currently selected hardware(ByteBlasterII) Select JTAG from Mode

Step 4 Turn on Program/configure. Or see figure below Click Start
See 7-segment status

SignalTap II Agenda SignalTap II Overview & Features
Using SignalTap II Interface Advanced Triggering

SignalTap II ELA Captures the Logic State of FPGA Internal Signals Using a Defined Clock Signal Gives Designers Ability to Monitor Buried Signals Connects to Quartus II through FPGA JTAG Pins Captures Real-Time Data Up to 200 Mhz Is Available for Free Installed with Full Subscription or Web Edition Installed with Stand-Alone Programmer

SignalTap II Device Support
Stratix & Stratix II Stratix GX Cyclone & Cyclone II Excalibur Mercury APEX II APEX 20K/E/C

How Does It Work? Configure ELA
Download ELA into FPGA along with Design ELA Samples Internal Signals Quartus II Communicates with ELA through JTAG

Stratix/Cyclone Sample Resource Usage
Number of Channels Logic Elements Trigger Level 1 Trigger Level 2 Trigger Level 3 8 316 371 426 32 566 773 981 256 2900 4528 6156 Number of Channels M4Ks Based on Sample Depth 256 512 2K 8K 32K 8 < 1 1 4 16 64 32 2 128

Modes of Operation Three Different Configurations
Internal RAM ELA Configuration Debug Port ELA Configuration Hybrid Approach Provides Flexibility Based on Available Device Resources Memory Resources Are Limited Use Debug Port Configuration Pin Resources Are Limited Use Internal RAM Configuration

Supported Download Cables
USB Blaster USB Port Cable ByteBlaster™ II Parallel Port Cable ByteBlasterMV™ Parallel Port MasterBlaster™ USB / Serial Port Cable

SignalTap II Key Features
Setup Data Triggering Data Capture Data Analysis

Setup Features Up to 1024 Data Channels
Data Triggering Data Capture Data Analysis Up to 1024 Data Channels Multiple Analyzers in One Device Supports Analysis of Multiple Clock Domains Each Analyzer Can Run Simultaneously Resource Usage Estimation Incremental Design Support

Data Triggering Features
Setup Data Triggering Data Capture Data Analysis Up to 10 Trigger Levels Per Channel Allows Application of Simple (Basic) & Complex (Advanced) Triggering Schemes Defines a Sequential Pattern of Logic Conditions Each Trigger Level is Logically ANDED If (L1 & L2 ... & L10) == TRUE  Data Capture

Data Triggering Features (Cont.)
Setup Data Triggering Data Capture Data Analysis Three Main Trigger Positions Trigger Input Setup External Trigger to Trigger the Analyzer Trigger Output Signifies Trigger Event Occurred with SignalTap II Use One ELA’s Trigger Output as Trigger Input for Another TIME Old Samples New Samples trigger Samples Captured Data Triggering

Data Capture Features Up to 128K Samples Per Channel
Setup Data Triggering Data Capture Data Analysis Up to 128K Samples Per Channel Increases Chance of Catching Target Event Two Methods of Data Acquisition Circular Segmented Mnemonic Tables Create User-Defined Labels for Bit Sequences (Ex. State Machine)

SignalTap II Design Flow
Use SignalTap II File (.STP) Use Quartus II GUI STP Separate from Design Files Use Quartus II MegaWizard Instantiate Directly into HDL

Using STP File Create .STP File Save .STP File & Compile with Design
Assign Sample Clock Specify Sample Depth Assign Signals to STP File Specify Triggering Setup JTAG Save .STP File & Compile with Design Program Device Acquire Data

1) Creating a New .STP File
To Create a .STP File Method 1 Select the in Quartus II Method 2 Select New (File Menu) Other Files SignalTap II File Default File Name Will Be STP1.stp

Main .STP File Components
JTAG Chain Configuration .STP File Instance Manager Waveform Viewer Signal Configuration

Instance Manager Instance Manager Selects Current ELA to Setup/View
Displays the Current Status of each Instance Displays Size (Resource Usage) of ELA

Assign Sample Clock Use Global Clock for Best Results
Data Written to Memory on Every Sample Clock Rising Edge Clock Signal Cannot Be Monitored as Data External Clock Pin Created Automatically if Clock Unassigned auto_stp_external_clock ELA Expects External Signal to be Connected to Clock Pin

Specify Sample Depth Sample Depth
Set Number of Samples Stored for each Data Signal 0 to 128K Sample Depth 0 Selected When External Analyzer Is Used Select RAM Type for Stratix & Stratix II Devices Useful when Preserving a Specific Memory Type is Necessary

Data Capture Circular Segmented Specify Trigger Position
Pre Center Post Continuous Segmented Specify Segment Depth

Triggering Trigger Levels Trigger-In Trigger-Out
Indicate up to 10 Trigger Conditions Trigger-In Any I/O Pin Can Trigger the SignalTap II Analyzer Generates auto_stp_trigger_in_n Pin Trigger-Out Indicates When a Trigger Pattern Occurs Generates auto_stp_trigger_out_n Pin Delayed 4 Clock Cycles after Actual Trigger Event

Waveform Viewer Setup Tab Describes the Signal Settings
Data Signals vs. Trigger Signals Sets up Each Triggering Level (L1 – L10) Data Tab Displays Captured Data

STP File Waveform Viewer
Setup Tab Data Tab

Basic Triggering All Signals Must Be True for Level to Cause Data Capture Right-Click to Set Value

Debug Port Routes Data Signals to Spare I/O Pins for Capture by External Logic Analyzer Quartus II Automatically Generates auto_stp_debug_out_m_n Pin m Represents the Instance Number of the Analyzer n Represents the Order the Debug Port Pin Occurs in the Signal List

Mnemonic Table Allows a Set of Bit Patterns to Be Assigned User-Defined Names Right-Click in the Setup View of an STP File & Select Mnemonic Setup Select Add Table Select Add Entry Ex. State Machines or Decoders/Encoders

JTAG Chain Configuration
Select Programming Hardware Scan Chan Button Automatically Determines Devices Physically Connected to the Chain Detects Non-Altera Devices & Displays Them as Unknown

2) Save .STP File & Compile
SignalTap II Logic Analyzer Control in Compiler Settings Assignments  Settings Specify the STP File to Compile with Project

3) Program Device(s) Use Quartus II Programmer or STP File
Program Button in the SignalTap II Interface Only Configures the Selected Device in Chain Use Quartus II Programmer to Program Multiple Devices Can Create a STP File for each Device in the JTAG Chain

4) Acquire Data SignalTap II Toolbar & STP File Controls Run Autorun
Stop Read Data (Reads in Data from Last Analysis)

Displaying Acquired Data
Format in Time or Sample Number Display Signal as Bar or Line Chart Export to Other Tools for Viewing or Analysis (File Menu) Creates .VWF, .TBL, .CSV, .VCD, .JPG or .BMP File

Using STP File Review Create .STP File
Assign Sample Clock Specify Sample Depth Assign Signals to STP File Specify Triggering Setup JTAG Save .STP File & Compile with Design Program Device Acquire Data

Recompilation Recompilation Required
Addition/Removal of Instance, Data or Trigger Modifying the Sample Clock or Buffer Depth Enabling/Modifying Trigger-In/Trigger-Out Enabling the Debug Port Lock Mode Prevents Changes Requiring Recompilation

Reducing Recompilation Times
Incremental Compilation Maintains Design Synthesis & Placement Recompiles Only Logic Analyzer Change SignalTap II Configuration without Affecting Existing Logic Incremental Routing Allows Switching Trigger & Data Nodes without Full Recompilation Cannot Be Used Together in 5.0 Use Incremental Compilation First, Switch to Routing Will Be Supported in Future Version of Quartus II

SignalTap II Incremental Compilation
Enable Full Incremental Compilation Any User-Defined Partitions Must Be Removed (5.0 Limitation) Set Netlist Type of Top-Level Partition to Post-Fit Assignments Menu

SignalTap II Incremental Compilation
Compile Design Enable SignalTap II Incremental Compilation Only Post Fitting Nodes Can Be Incrementally Compiled Quartus II Will Automatically Convert Pre-Synthesis Nodes to Post-Fitting

SignalTap II Incremental Routing
Enable Smart Recompilation Manually Set the Number of Allocated Nodes Nodes Acts as Place Holders for Real Signals that Can Be Added Later Auto Creates Enough Nodes for Current Number of Data/Triggers

SignalTap II Incremental Routing
Add Post-Fitting nodes to STP file SignalTap II: Post-Fitting Nodes Always Incrementally Routed SignalTap II: Pre-Synthesis Nodes Always Cause Full Recompilation if Added Later Benefit of Enabling Incremental Routing on Pre-Synthesis Nodes is They Can Be Removed & Replaced with Post-fitting Nodes without Total Recompilation Pre-Synthesis Nodes Post-fitting Nodes

Quartus II Netlist Optimization
New Synthesis Optimization Features Do Not Work Well with SignalTap II SignalTap II Nodes may Disappear Register Re-timing & WYSIWYG Re-Synthesis Should be Disabled if SignalTap II is Used Set Netlist Optimizations Logic Option to Never Allow on Entities which Have SignalTap II Nodes

Performance Preservation
SignalTap II can Potentially Effect the Performance of a Design Routing and/or Placement Can Change Possible Solution Back-Annotate Design before Adding SignalTap II See Quartus II Handbook, Volume 3, Chapter 10 for More Suggestions

Thank You

Quartus II Basic Training

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