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Copyright © 2005 Altera Corporation Quartus II Basic Training
Copyright © 2005 Altera Corporation 2 Structured ASIC HardCopy ® II, HardCopy Stratix High & Medium Density FPGAs Stratix II, Stratix, APEX II, APEX 20K, & FLEX 10K ® Low-Cost FPGAs Cyclone II & Cyclone FPGAs with Clock Data Recovery Stratix II GX CPLDs MAX II, MAX 7000 & MAX 3000 Embedded Processor Solutions Nios II Configuration Devices Serial (EPCS) & Enhanced (EPC) Programmable Logic Families
Copyright © 2005 Altera Corporation 3 MAX 7000A & MAX 3000A Family Overview Useable Gates Macrocells Maximum User I/O Pins t PD (ns) f CNT (MHz) t SU (ns) t CO1 (ns) Parameter 1, , , , EPM3032AEPM3064AEPM3128AEPM3256AEPM3512A MAX 3000A , , , , EPM7032AEEPM7064AEEPM7128AEEPM7256AEEPM7512AE MAX 7000A
Copyright © 2005 Altera Corporation 4 Complete Voltage Portfolio MAX 7000SMAX 7000AE MAX 3000A MAX 7000B Performance Leader Feature Leader Wide Range of Package Offerings Industrial-Grade Offerings High Performance Feature Leader Wide Range of Package Offerings Price Leader Feature & Package Subset of MAX 7000AE High Performance Feature Leader Wide Range of Package Offerings 5.0 V2.5 V3.3 V
Copyright © 2005 Altera Corporation 5 MAX Device Block Diagram
Copyright © 2005 Altera Corporation 6 MAX Macrocell Global Clock Global Clear 36 Programmable Interconnect Signals 16 Expander Product Terms to I/O Control Block 7000 has two Global Clock Product- Term Select Matrix VCC D ENA PRn CLRn Q Clear Select Clock/ Enable Select Register Bypass Shared Logic Expanders Parallel Logic Expanders (from other MCs) to PIA Programmable Register
Copyright © 2005 Altera Corporation 7 MAX II: The Lowest-Cost CPLD Ever New Logic Architecture 1/2 the Cost 1/10 the Power Consumption 2X the Performance 4X the Density Non-Volatile, Instant-On Supports 3.3-, 2.5- & 1.8-V Supply Voltages Breakthrough Technology to Expand the Market
Copyright © 2005 Altera Corporation 8 Flexible Supply Voltage On-Chip Voltage Regulator Accepts 3.3-, 2.5- & 1.8-V Supply Inputs Internally Converted to 1.8-V Core Voltage 2.5 V 3.3 V 1.8 V Convenience of 3.3 V with the Power & Performance of 1.8 V
Copyright © 2005 Altera Corporation 9 MAX II Device Family Device Logic Elements (LEs) Typical Macro- cells User I/O Pins Speed Grades Fastest t pd1 (ns) User Flash Memory (bits) EPM , 4, 54.78,192 EPM , 4, 55.58,192 EPM12701, , 4, 56.38,192 EPM22102,2101, , 4, 57.18,192
Copyright © 2005 Altera Corporation 10 Device 100-Pin TQFP mm Pitch 16 x 16 mm 144-Pin TQFP 0.5-mm Pitch 22 x 22 mm 256-Pin FBGA mm Pitch 17 x 17 mm 324-Pin FBGA 1.0-mm Pitch 19 x 19 mm EPM24080 EPM EPM EPM MAX II Packaging & User I/O Pins Denotes Vertical Migration Notes: 1. TQFP: thin quad flat pack 2. FineLine BGA ® package (1.0-mm pitch)
Copyright © 2005 Altera Corporation 11 New Small Packages Packages minimize PCB area and optimize ease-of-use Partial arrays allow for 2 layer PCB break out T mm TQFP 16x16mm Partial M mm MBGA 6x6mm Partial M mm MBGA 11x11mm F mm FBGA 17x17mm New Packages
Copyright © 2005 Altera Corporation 12 MAX II Architecture Staggered I/O Pads User Flash Memory Logic Elements (LEs) JTAG & Control Circuitry Configuration Flash Memory
Copyright © 2005 Altera Corporation 13 MAX II Logic Element (LE) data1 addnsub data2 data3 4-Input LUT 4-Input LUT cin data4 Register Chain Reg sloadsclearaload clock ena aclr Row, Column & Direct Link Routing Local Routing LUT Chain Register Chain
Copyright © 2005 Altera Corporation 14 User Flash Memory Feature Flash Memory Storage Bank 8,192 Bits Per Device Interface to SPI, I 2 C, Parallel, or Proprietary Buses Applications Store Revision & Serial Number Data Store Boot-Up & Configuration Data Industry First! User Flash Memory Block
Copyright © 2005 Altera Corporation 15 MAX & MAX II Comparison ParameterMAXMAX II Process Technology0.3-um EEPROM0.18-um Flash Logic ArchitectureProduct TermLook-Up Table (LUT) Density Range32 to 512 Macrocells128 to 2210 Macrocells (240 to 2,210 LEs) Routing ArchitectureGlobalRow & Column On-Chip Flash MemoryNone8 Kbits Maximum User I/O Pins Supply Voltage5.0 V, 3.3 V, 2.5 V3.3 V/2.5 V, 1.8 V I/O Voltages5.0 V, 3.3 V, 2.5 V, 1.8 V3.3 V, 2.5 V, 1.8 V, 1.5 V Global Clock Networks2 per Device4 per Device Output Enables (OEs)6 to 10 per Device1 per I/O Pin Schmitt TriggersNone1 per I/O Pin
Copyright © 2005 Altera Corporation 16 What is Nios II ? Alteras Second Generation Soft-Core 32 Bit RISC Microprocessor Developed Internally By Altera Harvard Architecture Royalty-Free FPGA - Nios II Plus All Peripherals Written In HDL - Can Be Targeted For All Altera FPGAs - Synthesis Using Quartus II Integrated Synthesis Avalon Switch Fabric UART GPIO Timer SPI SDRAM Controller On-Chip ROM On-Chip RAM Nios II CPU Debug Cache
Copyright © 2005 Altera Corporation 17 Nios II Processor Architecture Classic Pipelined RISC Machine 32 General Purpose Registers 3 Instruction Formats 32-Bit Instructions 32-Bit Data Path Flat Register File Separate Instruction and Data Cache (configurable sizes) Tightly-Coupled Memory Options Branch Prediction 32 Prioritized Interrupts On-Chip Hardware (Multiply, Shift, Rotate) Custom Instructions JTAG-Based Hardware Debug Unit
Copyright © 2005 Altera Corporation 18 Problem: Reduce Cost, Complexity & Power Flash SDRAM CPU DSP I/O FPGA I/O CPU DSP Solution: Replace External Devices with Programmable Logic FPGA
Copyright © 2005 Altera Corporation 19 Problem: Reduce Cost, Complexity & Power Flash SDRAM Solution: Replace External Devices with Programmable Logic CPU is a Critical Control Function Required for System-Level Integration System On A Programmable Chip (SOPC) FPGA
Copyright © 2005 Altera Corporation 20 Licensing Nios II Delivered As Encrypted Megacore Licensed Via Feature Line In Existing Quartus II License File Consistent With General Altera Megacore Delivery Mechanism Enables Detection Of Nios II In Customer Designs (Talkback) No Nios II Feature Line (OpenCore Plus Mode) System Runs If Tethered To Host PC System Times Out If Disconnected from PC After ~ 1 hr Nios II Feature Line (Active Subscriber) Subscription and New Dev Kit Customers Obtain Licenses From Nios II CPU RTL Remains Encrypted Nios II Source License Available Upon Request On Case-By-Case Basis Included With Purchase Of Nios II ASIC License
Copyright © 2005 Altera Corporation Quartus II Basic Training Quartus II Development System Feature Overview Quartus II Development System Feature Overview
Copyright © 2005 Altera Corporation 22 Software & Development Tools Quartus II All Stratix, Cyclone & Hardcopy Devices APEX II, APEX 20K/E/C, Excalibur, & Mercury Devices FLEX 10K/A/E, ACEX 1K, FLEX 6000 Devices MAX II, MAX 7000S/AE/B, MAX 3000A Devices Quartus II Web Edition Free Version Not All Features & Devices Included See for Feature Comparisonwww.altera.com MAX+PLUS ® II All FLEX, ACEX, & MAX Devices
Copyright © 2005 Altera Corporation Quartus II Development System Fully-Integrated Design Tool Multiple Design Entry Methods Logic Synthesis Place & Route Simulation Timing & Power Analysis Device Programming
Copyright © 2005 Altera Corporation 24 Typical PLD Design Flow Synthesis - Translate Design into Device Specific Primitives - Optimization to Meet Required Area & Performance Constraints - Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA, Quartus II Design Specification Place & Route - Map Primitives to Specific Locations inside Target Technology with Reference to Area & Performance Constraints - Specify Routing Resources to Be Used Design Entry/RTL Coding - Behavioral or Structural Description of Design RTL Simulation - Functional Simulation (Modelsim ®, Quartus II) - Verify Logic Model & Data Flow (No Timing Delays) LE M512 M4K I/O
Copyright © 2005 Altera Corporation 25 Typical PLD Design Flow Timing Analysis - Verify Performance Specifications Were Met - Static Timing Analysis Gate Level Simulation - Timing Simulation - Verify Design Will Work in Target Technology PC Board Simulation & Test - Simulate Board Design - Program & Test Device on Board - Use SignalTap II for Debugging t clk
Copyright © 2005 Altera Corporation 26 Design Entry Methods Quartus II Text Editor AHDL VHDL Verilog Schematic Editor Block Diagram File Graphic Design File Memory Editor HEX MIF 3 rd -Party EDA Tools EDIF HDL VQM Mixing & Matching Design Files Allowed Top-level design files can be schematic, HDL or 3 rd - Party Netlist File Block File Symbol File Text File Text File Text File Imported from 3 rd -Party EDA tools Generated within Quartus II Text File Text File.v, vlg,.vhd,.vhdl, vqm.edf.edif.v.vhd.tdf.bsf.bdf.gdf Top- Level File
Copyright © 2005 Altera Corporation Quartus II Basic Training Quartus II Quick Start LAB1
Copyright © 2005 Altera Corporation 28 Objectives Create a project using the New Project Wizard Name the project Add design files Pick a device
Copyright © 2005 Altera Corporation 29 Step 1 (Setup Project for QII5_1) Under File, Select New Project Wizard…. A new window appears. If an Introduction screen appears, click Next.
Copyright © 2005 Altera Corporation 30 Step 2 (Setup Project for QII5_1) Page 1 of the wizard should be completed with the following working directory for this project \ Dsp_7_segment \ name of project Dsp_7_segment top-level design entity Dsp_7_segment Copy state_machine.v and past in Dsp_7_segment Click Next to advance to the Project Wizard: Add Files [page 2 of 5].
Copyright © 2005 Altera Corporation 31 Step 3 (Setup Project for QII5_1) Using the browse button, select state_machine.v Add to the project. Click Next.
Copyright © 2005 Altera Corporation 32 Step 4 (Setup Project for QII5_1) On page 3, select Stratix as the Family. Also, in the Filters section, set Package to FBFA, Pin count to 780, and Speed grade to 5. Select the EP1S25F780C5 device from the Available devices: window. Click Next.
Copyright © 2005 Altera Corporation 33 Step 5 (Setup Project for QII5_1) On page 4, you can specify any third party EDA tools you may be using along with Quartus II. Since these exercises will be done entirely within Quartus II, click Next.
Copyright © 2005 Altera Corporation 34 Step 6 (Setup Project for QII5_1) The summary screen appears as shown. Click Finish. The project is now created.
Copyright © 2005 Altera Corporation Quartus II Basic Training Quartus II Quick Start LAB2
Copyright © 2005 Altera Corporation 36 Objectives Create a counter using the MegaWizard Plug-in Manager Build a design using the schematic editor Analyze and elaborate the design to check for errors
Copyright © 2005 Altera Corporation 37 Step 1 Create schematic file Select File New and select Block Diagram/Schematic File. Click OK. Select File Save As and save the file as \Dsp_7_segment\ Dsp_7_segment.bdf
Copyright © 2005 Altera Corporation 38 Step 2 Build an 23 bits counter using the MegaWizard Plug-in Manager 1.Choose Tools MegaWizard Plug-In Manager. In the window that appears, select Create a new custom megafunction variation. Click on Next. 2.On page 2a of the MegaWizard expand the arithmetic folder and select LPM_COUNTER. 3.Choose Verilog HDL output For the name of the output file, type timer_1s. Click on Next
Copyright © 2005 Altera Corporation 39 Step 3 1.Set the output bus to 27 bits. For the remaining settings in this window, use the defaults that appear.. Select next 2..Turn on Modulus, with a count modulus of and key in Select finish
Copyright © 2005 Altera Corporation 40 Step 4 In the Graphic Editor, double-click in the screen so that the Symbol Window appears. Inside the symbol window, click on to expand the symbols defined in the Project folder. Double-click on timer_1s. Click the left mouse button to put down the symbol inside the schematic file.. The symbol for timer_1s now appears in the schematic.
Copyright © 2005 Altera Corporation 41 Step 5 1.From the File menu, open the file state_machine.v 2.From the File menu, go the Create/Update menu option and select Create Symbol Files for Current File. Click Yes to save changes to Dsp_7_segment.bdf. 3.Once Quartus II is finished creating the symbol, click OK. Close the state_machine.v file 4.In the Graphic Editor, double-click in the screen so that the Symbol Window appears again. Double-click on state_machine in the Project folder. Click OK... The symbol for state_machine now appears in the schematic.
Copyright © 2005 Altera Corporation 42 Step 6 Add Pins to the Design InputOutput sys_clk 7_out[6..0] resetDig1 For each of the pins listed in left Table, you must insert a pin and change its name 1.To place pins in the schematic file, go to Edit Insert Symbol OR double-click in any empty location of the Graphic Editor. 2.Browse to libraries primitives pin folder. Double-click on input or output Hint: To insert multiple pins select Repeat Insert Mode. 3.To rename the pins double-click on the pin name after it has been inserted. 4.Type the name in the Pin name(s) field and Click OK.
Copyright © 2005 Altera Corporation 43 Step 7 Connect the Pins and Blocks in the Schematic 1.In the left hand tool bar click on button to draw a wire and button to draw a bus. Another way to draw wires and busses is to place the cursor next to the port of any symbol. When you do this, the wire or bus tool will automatically appear. 2.Connect all of the pins and blocks as shown in the figure below
Copyright © 2005 Altera Corporation 44 Step 8 Save and check the schematic 1.Click on the Save button in the toolbar to save the schematic. 2.From the Project menu, select Add/Remove Files in Project. Click on the browse button to make sure the Dsp_7_segment.bdf, timer_1s and state_machine are added to the project. 3.From the Processing menu, select Start Start Analysis & Elaboration. Analysis and elaboration checks that all the design files are present and connections have been made correctly. 4.Click OK when analysis and elaboration is completed
Copyright © 2005 Altera Corporation Quartus II Basic Training Quartus II Quick Start LAB3
Copyright © 2005 Altera Corporation 46 Objectives Pin assignment Perform full compilation Build a design using the schematic editor How to Download programming file
Copyright © 2005 Altera Corporation 47 Step 1 1.Choose Assignments Assignment editor. 2.From the View menu, select Show All Know Pin Names. 3.Please click Pin in Category
Copyright © 2005 Altera Corporation 48 Step 2 1.Pls install DSP Development Kit Stratix edtion CD 2.Open ds_stratix_dsp_bd.pdf from C:\megacore\stratix_dsp_kit-v1.1.0\Doc 3.Check clk, pushbotton and seven segment display pin location from ds_stratix_dsp_bd.pdf 4.Key your pin number in location 5.Click on the Save button in the toolbar 6.From Assignments, select Device. Click Device & Pin options. Click Unused pins.Select As input tri-stated from Reserve all unused pins 7.From the Processing menu, select Start Compilation
Copyright © 2005 Altera Corporation 49 Step 3 1.From the Tools menu, select programmer 2.Click on Add File. Select Dsp_7_segment.sof. 3.Check Hardware Setup. Select your download cable on Currently selected hardware(ByteBlasterII) 4.Select JTAG from Mode
Copyright © 2005 Altera Corporation 50 Step 4 1.Turn on Program/configure. Or see figure below 2.Click Start 3.See 7-segment status
Copyright © 2005 Altera Corporation 51 SignalTap II Agenda SignalTap II Overview & Features Using SignalTap II Interface Advanced Triggering
Copyright © 2005 Altera Corporation 52 SignalTap II ELA Captures the Logic State of FPGA Internal Signals Using a Defined Clock Signal Gives Designers Ability to Monitor Buried Signals Connects to Quartus II through FPGA JTAG Pins Captures Real-Time Data Up to 200 Mhz Is Available for Free Installed with Full Subscription or Web Edition Installed with Stand-Alone Programmer
Copyright © 2005 Altera Corporation 53 SignalTap II Device Support Stratix & Stratix II Stratix GX Cyclone & Cyclone II Excalibur Mercury APEX II APEX 20K/E/C
Copyright © 2005 Altera Corporation 54 How Does It Work? 1.Configure ELA 2.Download ELA into FPGA along with Design 3.ELA Samples Internal Signals 4.Quartus II Communicates with ELA through JTAG
Copyright © 2005 Altera Corporation 55 Stratix/Cyclone Sample Resource Usage Number of Channels Logic Elements Trigger Level 1Trigger Level 2Trigger Level Number of Channels M4Ks Based on Sample Depth K8K32K 8<
Copyright © 2005 Altera Corporation 56 Modes of Operation Three Different Configurations Internal RAM ELA Configuration Debug Port ELA Configuration Hybrid Approach Provides Flexibility Based on Available Device Resources Memory Resources Are Limited Use Debug Port Configuration Pin Resources Are Limited Use Internal RAM Configuration
Copyright © 2005 Altera Corporation 57 Supported Download Cables USB Blaster USB Port Cable ByteBlaster II Parallel Port Cable ByteBlasterMV Parallel Port MasterBlaster USB / Serial Port Cable
Copyright © 2005 Altera Corporation 58 SignalTap II Key Features Setup Data Triggering Data Capture Data Analysis
Copyright © 2005 Altera Corporation 59 Setup Features Up to 1024 Data Channels Multiple Analyzers in One Device Supports Analysis of Multiple Clock Domains Each Analyzer Can Run Simultaneously Resource Usage Estimation Incremental Design Support Setup Data Triggering Data Capture Data Analysis
Copyright © 2005 Altera Corporation 60 Data Triggering Features Up to 10 Trigger Levels Per Channel Allows Application of Simple (Basic) & Complex (Advanced) Triggering Schemes Defines a Sequential Pattern of Logic Conditions Each Trigger Level is Logically ANDED If (L1 & L2... & L10) == TRUE Data Capture Setup Data Triggering Data Capture Data Analysis
Copyright © 2005 Altera Corporation 61 Data Triggering Features (Cont.) Three Main Trigger Positions Trigger Input Setup External Trigger to Trigger the Analyzer Trigger Output Signifies Trigger Event Occurred with SignalTap II Use One ELAs Trigger Output as Trigger Input for Another Data Triggering Setup Data Triggering Data Capture Data Analysis TIME Old Samples New Samples trigger Samples Captured
Copyright © 2005 Altera Corporation 62 Data Capture Features Up to 128K Samples Per Channel Increases Chance of Catching Target Event Two Methods of Data Acquisition 1.Circular 2.Segmented Mnemonic Tables Create User-Defined Labels for Bit Sequences (Ex. State Machine) Setup Data Triggering Data Capture Data Analysis
Copyright © 2005 Altera Corporation 63 SignalTap II Design Flow 1)Use SignalTap II File (.STP) Use Quartus II GUI STP Separate from Design Files 2)Use Quartus II MegaWizard Instantiate Directly into HDL
Copyright © 2005 Altera Corporation 64 Using STP File 1.Create.STP File Assign Sample Clock Specify Sample Depth Assign Signals to STP File Specify Triggering Setup JTAG 2.Save.STP File & Compile with Design 3.Program Device 4.Acquire Data
Copyright © 2005 Altera Corporation 65 1) Creating a New.STP File To Create a.STP File Method 1 Select the in Quartus II Method 2 Select New (File Menu) Other Files SignalTap II File Default File Name Will Be STP1.stp
Copyright © 2005 Altera Corporation 66 Main.STP File Components Signal Configuration JTAG Chain Configuration Waveform Viewer.STP File Instance Manager
Copyright © 2005 Altera Corporation 67 Instance Manager Selects Current ELA to Setup/View Displays the Current Status of each Instance Displays Size (Resource Usage) of ELA
Copyright © 2005 Altera Corporation 68 Assign Sample Clock Use Global Clock for Best Results Data Written to Memory on Every Sample Clock Rising Edge Clock Signal Cannot Be Monitored as Data External Clock Pin Created Automatically if Clock Unassigned auto_stp_external_clock ELA Expects External Signal to be Connected to Clock Pin
Copyright © 2005 Altera Corporation 69 Specify Sample Depth Sample Depth Set Number of Samples Stored for each Data Signal 0 to 128K Sample Depth 0 Selected When External Analyzer Is Used Select RAM Type for Stratix & Stratix II Devices Useful when Preserving a Specific Memory Type is Necessary
Copyright © 2005 Altera Corporation 70 Data Capture Circular Specify Trigger Position Pre Center Post Continuous Segmented Specify Segment Depth
Copyright © 2005 Altera Corporation 71 Triggering Trigger Levels Indicate up to 10 Trigger Conditions Trigger-In Any I/O Pin Can Trigger the SignalTap II Analyzer Generates auto_stp_trigger_in_n Pin Trigger-Out Indicates When a Trigger Pattern Occurs Generates auto_stp_trigger_out_n Pin Delayed 4 Clock Cycles after Actual Trigger Event
Copyright © 2005 Altera Corporation 72 Waveform Viewer Setup Tab Describes the Signal Settings Data Signals vs. Trigger Signals Sets up Each Triggering Level (L1 – L10) Data Tab Displays Captured Data
Copyright © 2005 Altera Corporation 73 STP File Waveform Viewer Setup Tab Data Tab
Copyright © 2005 Altera Corporation 74 Basic Triggering Right-Click to Set Value All Signals Must Be True for Level to Cause Data Capture
Copyright © 2005 Altera Corporation 75 Debug Port Routes Data Signals to Spare I/O Pins for Capture by External Logic Analyzer Quartus II Automatically Generates auto_stp_debug_out_m_n Pin m Represents the Instance Number of the Analyzer n Represents the Order the Debug Port Pin Occurs in the Signal List
Copyright © 2005 Altera Corporation 76 Mnemonic Table Allows a Set of Bit Patterns to Be Assigned User- Defined Names Right-Click in the Setup View of an STP File & Select Mnemonic Setup Select Add Table Select Add Entry Ex. State Machines or Decoders/Encoders
Copyright © 2005 Altera Corporation 77 JTAG Chain Configuration Select Programming Hardware Scan Chan Button Automatically Determines Devices Physically Connected to the Chain Detects Non-Altera Devices & Displays Them as Unknown
Copyright © 2005 Altera Corporation 78 2) Save.STP File & Compile SignalTap II Logic Analyzer Control in Compiler Settings Assignments Settings Specify the STP File to Compile with Project
Copyright © 2005 Altera Corporation 79 3) Program Device(s) Use Quartus II Programmer or STP File Program Button in the SignalTap II Interface Only Configures the Selected Device in Chain Use Quartus II Programmer to Program Multiple Devices Can Create a STP File for each Device in the JTAG Chain
Copyright © 2005 Altera Corporation 80 4) Acquire Data SignalTap II Toolbar & STP File Controls Run Autorun Stop Read Data (Reads in Data from Last Analysis)
Copyright © 2005 Altera Corporation 81 Displaying Acquired Data Display Signal as Bar or Line Chart Export to Other Tools for Viewing or Analysis (File Menu) Creates.VWF,.TBL,.CSV,.VCD,.JPG or.BMP File Format in Time or Sample Number
Copyright © 2005 Altera Corporation 82 Using STP File Review 1.Create.STP File Assign Sample Clock Specify Sample Depth Assign Signals to STP File Specify Triggering Setup JTAG 2.Save.STP File & Compile with Design 3.Program Device 4.Acquire Data
Copyright © 2005 Altera Corporation 83 Recompilation Recompilation Required Addition/Removal of Instance, Data or Trigger Modifying the Sample Clock or Buffer Depth Enabling/Modifying Trigger-In/Trigger-Out Enabling the Debug Port Lock Mode Prevents Changes Requiring Recompilation
Copyright © 2005 Altera Corporation 84 Reducing Recompilation Times Incremental Compilation Maintains Design Synthesis & Placement Recompiles Only Logic Analyzer Change SignalTap II Configuration without Affecting Existing Logic Incremental Routing Allows Switching Trigger & Data Nodes without Full Recompilation Cannot Be Used Together in 5.0 Use Incremental Compilation First, Switch to Routing Will Be Supported in Future Version of Quartus II
Copyright © 2005 Altera Corporation 85 SignalTap II Incremental Compilation 1)Enable Full Incremental Compilation Any User-Defined Partitions Must Be Removed (5.0 Limitation) 2)Set Netlist Type of Top-Level Partition to Post-Fit Assignments Menu
Copyright © 2005 Altera Corporation 86 SignalTap II Incremental Compilation 3)Compile Design 4)Enable SignalTap II Incremental Compilation Only Post Fitting Nodes Can Be Incrementally Compiled Quartus II Will Automatically Convert Pre-Synthesis Nodes to Post-Fitting
Copyright © 2005 Altera Corporation 87 SignalTap II Incremental Routing 1)Enable Smart Recompilation 2)Manually Set the Number of Allocated Nodes Nodes Acts as Place Holders for Real Signals that Can Be Added Later Auto Creates Enough Nodes for Current Number of Data/Triggers
Copyright © 2005 Altera Corporation 88 SignalTap II Incremental Routing 3)Add Post-Fitting nodes to STP file SignalTap II: Post-Fitting Nodes Always Incrementally Routed SignalTap II: Pre-Synthesis Nodes Always Cause Full Recompilation if Added Later Benefit of Enabling Incremental Routing on Pre-Synthesis Nodes is They Can Be Removed & Replaced with Post-fitting Nodes without Total Recompilation Pre-Synthesis Nodes Post-fitting Nodes
Copyright © 2005 Altera Corporation 89 Quartus II Netlist Optimization New Synthesis Optimization Features Do Not Work Well with SignalTap II SignalTap II Nodes may Disappear Register Re-timing & WYSIWYG Re-Synthesis Should be Disabled if SignalTap II is Used Set Netlist Optimizations Logic Option to Never Allow on Entities which Have SignalTap II Nodes
Copyright © 2005 Altera Corporation 90 Performance Preservation SignalTap II can Potentially Effect the Performance of a Design Routing and/or Placement Can Change Possible Solution Back-Annotate Design before Adding SignalTap II See Quartus II Handbook, Volume 3, Chapter 10 for More Suggestions
Copyright © 2005 Altera Corporation 91 Thank You
© 2005 Altera Corporation © 2006 Altera Corporation Simulation with Mentor Graphics ModelSim.
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