1. Date of download: 10/13/2017
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From: Experimental Characterization of the Vertical and Lateral Heat Transfer in Three-Dimensional Stacked Die Packages
J. Electron. Packag. 2016;138(1): doi: /
Figure Legend:
Left: Interdie thermal resistance map Rdd (K/W) for the full chip size (32 × 32 cells). Right: Schematic of the location of μbumps (6 × 6 array per cell) in the die–die interface and Cu pillars in the bottom die–package substrate interface (two pillars on the diagonal per cell) for a 1/16 part of the chip size (8 × 8 cells).