1. Chapter 6 Field effect transistor Ir. Dr. Rosemizi Abd Rahim 1 Ref: Electronic Devices and Circuit Theory, 10/e, Robert L. Boylestad and Louis Nashelsky

2. Objectives Explain the operation and characteristics of junction field effect transistors (JFET). Understand JFET parameters Discuss and analyze how JFETs are biased Explain the operation and characteristics of metal oxide semiconductor field effect transistors (MOSFET) Discuss and analyze how MOSFET are biased 2

3. Introduction FET – a three-terminal voltage-controlled device used in amplification and switching application. Field effect transistors controls current by voltage applied to the gate. The FET’s major advantage over the BJT is high input resistance. 2 basic type of FET: JFET - Junction FET MOSFET – Metal Oxide Semiconductor FET 3

4. JFET The junction field effect transistor, like a BJT, controls current flow. The difference is the way this is accomplished. The JFET uses voltage to control the current flow. As you will recall the transistor uses current flow through the base-emitter junction to control current. JFETs can be used as an amplifier just like the BJT. V GG voltage levels control current flow in theV DD, R D circuit. 4

5. JFET The terminals of a JFET are the source (S), gate (G), and drain (D). A JFET can be either p channel or n channel. 5

6. JFET V DD provide a drain-to-source voltage. V GG sets the reverse-bias voltage between gate and source. JFET is always operated with gate-source pn junction reverse-biased. Reverse-biasing of the gate-source junction with a –ve gate voltage produces a depletion region along pn junction, which extends into the n channel thus increases its resistance by restricting the channel width. The channel width and the channel resistance can be controlled by varying the gate voltage, thereby controlling the amount of drain current, ID. 6

7. JFET Biasing Gate-to-source junction of JFET always reverse-biased under normal condition. Gate-to-source junction never allowed to become forward-biased because the gate material is not designed to handle any significant amount of current  may destroy the component. The fact gate is always reverse-biased leads to important feature  JFET has high gate input impedance; typically in high megaohm range. This feature result to JFET extensively being used in integrated circuits. Low current draw helps IC remain cool, thus allowing more components to be placed in a smaller physical area. 7

8. JFET Characteristics and Parameters Let’s first take a look at the effects with a V GS of 0V. This is produced by shorting the gate to source junction. 8

9. JFET Drain Curve 9

10. Refer to JFET drain curve from point A to B, I D increases proportionally with increases of V DD (V DS increases as V DD increases). In this area, the channel resistance is essentially constant because the depletion region is not large enough to have significant effect. [V=IR] This is called the ohmic region (point A to B) because V DS and I D are related by Ohm’s Law. 10 JFET Drain Curve

11. At point B, the curve levels off and I D becomes constant. The point when I D ceases to increase regardless of V DD increases is called the pinch-off voltage, V P (point B). This current is called maximum drain current (I DSS ) and always specified for the condition, V GS =0V. This area is called constant-current area. Breakdown (point C) occur when I D begins to increase rapidly with any increase in V DS. This of course undesirable, so JFETs operation is always well below this value. 11 JFET Drain Curve

12. JFET Characteristics and Parameters From this set of curves you can see with increased voltage applied to the gate, I D decrease and JFET reaches pinch-off at values of V DS less than V P. 12

13. JFET Characteristics and Parameters 13

14. JFET Characteristics and Parameters 14

15. JFET Characteristics and Parameters We know that as V GS is increased I D will decrease. The point that I D ceases decrease is called cutoff. The amount of V GS required to do this is called the cutoff voltage (V GS(off ) ). The more negative V GS, the smaller I D becomes. When V GS has sufficiently large negative value, I D is reduced to zero. It is interesting to note that pinch-off voltage (V p ) and cutoff voltage (V GS(off) ) are both the same value only opposite polarity. 15

16. JFET Transfer Characteristic For n-channel JFET, V GS(off) is negative and for p-channel, V GS(off) is positive. Bottom end of the curve is at a point on V GS axis equal to V GS(off) and the top end of the curve is at a point on I D axis equal to I DSS (shorted-gate drain current rating of the device). The operating limits of JFET are: I D =0when V GS =V GS(off) I D =I DSS when V GS = 0 Transfer characteristic curve can be developed from drain characteristic curves by plotting values of I D for the values of V GS taken from the family of drain curves at pinch-off. 16

17. JFET Characteristics and Parameters The transfer characteristic curve illustrates the control V GS has on I D from cutoff (V GS(off) ) to pinchoff (V P ). Note the parabolic shape. The formula below can be used to determine drain current. All these values are usually available from data sheet. I D = I DSS (1 - V GS /V GS(off) ) 2 17

18. JFET Forward Transfer Conductance Forward transfer conductance, g m of JFETs is the changes in I D based on changes in V GS with V DS is constant. Forward transfer conductance referred to as g m = ∆I D /∆V GS. Unit is Siemens (s) The value is larger at the top of the curve (near V GS =0) but become smaller as you increase V GS (near V GS(off) ). 18

19. Transconductance At V GS =0, the parameter is known as minimum transfer conductance, g mo and can be calculated using this equation: g mo = 2I DSS /|V GS(off) | and g m = g mo (1 - V GS /V GS(off) ) g mo can be read from the datasheet as g fs or y fs and sometimes written as Forward Transfer Admittance. 19

20. JFET Input Resistance Since JFET is reverse-biased for operation, its input resistance becomes so large. This is an advantage of using JFET. Looking at the datasheet, you may calculate the resistance value by using the Gate Reverse Current I GSS. This internal input resistance can be calculated at different V GS : R IN =|V GS /I GSS | As I GSS increases with temperature, R IN will decrease. 20

21. JFET Biasing Circuit Just as we learned that the bi-polar junction transistor must be biased for proper operation, the JFET also must be biased for operation. Let’s look at some of the methods for biasing JFETs. In most cases the ideal Q-point will be the middle of the transfer characteristic curve which is about half of the I DSS. 4 types of bias method are self-bias, gate-bias, voltage-divider bias and current-source bias. 21

22. JFET Biasing- Self bias Self-bias is the most common type of biasing method for JFETs. Notice there is no voltage applied to the gate, V G =0V. However, the voltage from gate to source (V GS ) will be negative for n channel and positive for p channel to keep the junction reverse biased. 22

23. JFET Biasing- Self bias Uses a source resistor to help reverse bias JFET gate. The gate is returned to ground via R G, and R S has been added to source circuit. This voltage can be determined using the formulas below. I D = I S for all JFET circuits. V G =0 and V S =I D R S. V GS = V G - V S (n channel) V GS = 0-I D R S = -I D R S (p channel) V GS = 0-(-I D R S ) =I D R S 23

24. JFET Biasing – self bias Keep in mind that analysis of p-channel is the same as n- channel except for opposite polarity voltages. The drain voltage with respect to ground is: V D = V DD – I D R D Since V S = I D R S, V DS is: V DS = V D – V S = V DD – I D (R D +R S ) 24

25. JFET Biasing-self bias Setting the Q-point requires us to determine a value of R S that will give us the desired I D and V GS. The formula below shows the relationship. R S = | V GS /I D | For a desired value of V GS, I D can be determined from the either the transfer characteristic curve or more practically from the formula below. The data sheet provides the I DSS and V GS(off). I D = I DSS (1 - V GS /V GS(off) ) 2 25

26. JFET Midpoint Biasing-self bias- formula method Midpoint biasing- desirable to bias a JFET near the midpoint of its transfer characteristic curve where I D =I DSS / 2. I D is approximately one- half of I DSS when: V GS  V GS(off) /3.4 26

27. The value of R S needed to establish V GS can be determined by the relationship below. R S = | V GS /I D | To set the drain voltage at midpoint (VD=VDD/2), select a value of R D to produce the desired voltage drop. The value of R D needed can be determined by taking half of V DD and dividing it by I D. R D = (V DD /2)/I D JFET Midpoint Biasing-self bias- formula method 27

28. JFET Biasing- self-bias Remember the purpose of biasing is to set a dc operating point (Q-point). In a self- biasing type JFET circuit, the Q-point is determined by the given parameters of the JFET itself and values of R S and R D. Setting it at midpoint on the drain curve is most common. One thing not mentioned in the discussion is R G. It’s value is arbitrary large to prevent loading on the driving stage in a cascaded amplifier arrangement. 28

29. JFET Midpoint Biasing-self bias- graphical method The transfer characteristic curve along with other parameters can be used to determine the mid-point bias Q-point of a self-biased JFET circuit. First, establish dc load line by calculating V GS. V GS = -I D R S for I D =0 and I D =I DSS With 2 points (I D =0 and I D =I DSS ), draw dc load line on the transfer characteristic curve. The point where the two lines intersect gives us the I D and V GS (Q-point) needed for mid-point bias. Note that load line extends from V GS(off) (I D = 0A) to V P (I D = I DSS ) 29

30. JFET Midpoint Biasing-self bias- graphical method 30

31. JFET Biasing- voltage divider bias- formula Voltage-divider bias can also be used to bias a JFET. R 1 and R 2 are used to keep the gate-source junction in reverse bias. Operation is no different from self-bias. Determining V GS for a JFET voltage-divider circuit with givenV D can be calculated with the formulas below. Source voltage,V S = I D R S Gate voltage, V G =(R 2 /R 1 +R 2 )V DD Gate-to-source voltage.V GS =V G –V S Source voltage, V S = V G - V GS 31

32. JFET Biasing- voltage-divider bias - formula V S must be more +ve than V G in order to keep V GS reverse- biased (-ve value). Drain current, I D = (V DD – V D )/R D or Since I D =I S, then I D =V S /R S 32

33. JFET Biasing-voltage-divider bias- graphical In using the transfer characteristic curve to determine the approximate Q-point we must establish the 2 points for the load line. 1 st step draw dc load line: The first point is I D = 0 and V GS =V G. V S =I D R S =(0)R S =0V V GS =V G -V S =V G -0=V G The 2 nd point is for V GS =0, I D =(V G -V GS ) / R S = V G / R S I D =V G / R S and V GS =0. 33

34. The point at which the load line intersect with transfer characteristic curve is Q-point. Dc load line for JFET with voltage-divider bias 34 JFET Biasing-voltage-divider bias- graphical

35. JFET Biasing – Current Source Bias Current source bias  provides high Q-point stability by making value of I D independently of JFET. From figure, JFET drain current equals BJT collector current. I DQ = I C In this circuit, a BJT acts as the constant-current source because its emitter current is essentially constant if A FET can also be used as a constant current source. 35

36. JFET Biasing- Current source bias Advantage: provide the most stable Q- point value of I D. Disadvantage: circuit complexity makes it undesirable for most applications. 36

37. 37 JFET Biasing- Current source bias

38. JFET Biasing Transfer characteristics can vary for JFETs of the same type. This would adversely affect the Q-point for self-bias analysis. Q- point is much more stable using voltage-divider bias and current source bias. 38

39. The Ohmic Region The slope of the characteristic curve in the ohmic region is the dc drain-to- source conductance G DS of the JFET. Thus, the dc drain-to-source resistance is given by 39

40. The JFET as a Variable Resistance A JFET can be biased in either the active region or the ohmic region. JFETs are often biased in the ohmic region for use as a voltage controlled variable resistor. The control voltage is V GS, and it determines the resistance by varying the Q-point. 40

41. To bias a JFET in the ohmic region, the dc load line must intersect the characteristic curve in the ohmic region. Thus, to allows V DS to control R DS, the dc saturation current ID(sat), is set much less than I DSS so that the load line intersects most of the characteristic curves in the ohmic region. The JFET as a Variable Resistance 41

42. The JFET as a Variable Resistance Figure shows the operating region expanded with three Q-points shown (Q 0, Q 1, and Q 2 ), depending on V GS. As you move along the load line in the ohmic region, the value of R DS varies as the Q-point falls successively on curves with different slopes. The Q-point is moved along the load line by varying 42

43. The JFET as a Variable Resistance As this happens, the slope of each successive curve is less than the previous one. A decrease in slope corresponds to less I D and more V DS, which implies an increase in R DS. This change in resistance can be exploited in a number of applications where voltage control of a resistance is useful. ***R DS is the DC drain to source resistance Q0: ID= 0.270mA, VDS=0.23V Q1: ID=0.250mA, VDS=0.33V Q2: ID=0.230mA, VDS=0.44V Q3: ID=0.210mA, VDS=0.56V 43

44. The JFET as a Variable Resistance 44

45. MOSFET The metal oxide semiconductor field effect transistor (MOSFET) is the second category of FETs. The difference is that there no pn junction structure instead gate of MOSFET is insulated from the channel by silicon dioxide layer. MOSFETs are static sensitive devices and must be handled by appropriate means. There are depletion MOSFETs (D-MOSFET) and enhancement MOSFETs (E- MOSFET). Note the difference in construction. The E-MOSFET has no structural channel. 45

46. D-MOSFET The D-MOSFET can be operated in depletion or enhancement modes. To be operated in depletion mode, a negative gate-to-source voltage is applied. With negative gate voltage, negative charges on the gate repel electrons from channel, leaving +ve ions in their place. N-channel is depleted of some electron, thus decreasing channel conductivity. 46

47. D-MOSFET To be operated in the enhancement mode the gate- to-source is made more positive, attracting more electrons into the channel for better current flow and thus enhancing the channel conductivity. Remember we are using n channel MOSFETs for discussion purposes. For p channel MOSFETs, polarities would change. 47

48. E-MOSFET The E-MOSFET or enhancement MOSFET can operate in only the enhancement mode. With a positive voltage above a threshold value on the gate, an induced channel of thin layer of –ve charges is created. The conductivity of channel is enhanced by increase VGS and thus pulling more electrons into channel area. 48

49. POWER MOSFET The lateral double diffused MOSFET (LDMOSFET) and the V-groove MOSFET (VMOSFET) are specifically designed for high power applications. LDMOSFET VMOSFET 49

50. POWER MOSFET Dual gate MOSFETs have two gates which helps control unwanted capacitive effects at high frequencies. 50

51. MOSFET Characteristics and Parameters Since most of the characteristics and parameters of MOSFETs are the same as JFETs we will cover only the key differences. 51

52. D-MOSFET Characteristics and Parameters The D-MOSFET operate in either +ve or –ve gate voltages. The point on the curves where VGS=0 corresponds to IDSS. The point where ID=0 corresponds to VGS(off). As with JFET, VGS(off)=-V P. The equation to find drain current also the same as JFET: I D = I DSS (1 - V GS /V GS(off) ) 2 Remember n and p channel polarity differences. 52

53. E-MOSFET Characteristics and Parameters The E-MOSFET for all practical purposes does not conduct until V GS reaches the threshold voltage (V GS(th) ). I D when conducting can be determined by the formulas below. The constant K must first be determined from data sheet by taking I D(on) at any given value of VGS on a particular MOSFET. K = I D(on) /(V GS - V GS(th) ) 2 I D = K(V GS - V GS(th)) 53

54. MOSFET Biasing- zero bias The three ways to bias a MOSFET are zero-bias, voltage-divider bias, and drain-feedback bias. For D-MOSFET zero biasing as the name implies has no applied bias voltage to the gate. The input voltage swings it into depletion and enhancement mode. 54

55. Zero bias Since V GS =0 and I D =I DSS, the drain-to-source voltage is: V DS = V DD – I DSS R D The purpose of R G is to accommodate ac signal input by isolating it from ground as shown in figure (b) above. Since there is no dc gate current, R G does not affect the zero gate-to- source bias. 55

56. MOSFET Biasing- voltage divider bias For E-MOSFETs zero biasing cannot be used. Voltage-divider bias must be used to set the V GS greater than the threshold voltage (V GS(th) ). I D can be determined as follows. To determine V GS, normal voltage divider methods can be used. The following formula can be applied. V GS = (R 2 / (R 1 +R 2 ))V DD V DS = V DD - I D R D K = I D(on)/ (V GS - V GS(th) ) 2 I D = K(V GS -V GS(th) ) 2 V DS can be determined by application of Ohm’s law and Kirchhoff’s voltage law to the drain circuit. 56

57. MOSFET Biasing- drain feedback bias With drain-feedback bias there is no voltage drop across R G making V GS = V DS. With V GS given determining I D can be accomplished by the formula below. I D = (V DD – V DS )/R D 57