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Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 61 Lecture 6 Logic Simulation n What is simulation? n Design verification n Circuit modeling n True-value.

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Presentation on theme: "Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 61 Lecture 6 Logic Simulation n What is simulation? n Design verification n Circuit modeling n True-value."— Presentation transcript:

1 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 61 Lecture 6 Logic Simulation n What is simulation? n Design verification n Circuit modeling n True-value simulation algorithms n Compiled-code simulation n Event-driven simulation n Summary

2 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 62 Simulation Defined n Definition: Simulation refers to modeling of a design, its function and performance. n A software simulator is a computer program; an emulator is a hardware simulator. n Simulation is used for design verification: n Validate assumptions n Verify logic n Verify performance (timing) n Types of simulation: n Logic or switch level n Timing n Circuit n Fault

3 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 63 Simulation for Verification True-value simulation Specification Design (netlist) Input stimuli Computed responses Response analysis Synthesis Design changes

4 A 32-bit ripple-carry adder Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 64 1 0 0 0 0 0 1 1 1 1 1

5 Design verification Vectors for 4-bit adder circuit (functional correctness) Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 6 5 Delay Test for longest path : C0 C4, vector 2,6(3,7) C4: 0 1

6 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 66 5.2:Simulation for Test Evaluation Determines the Fault Coverage Produce a set of test vector

7 Test evaluation for single stuck at fault Four-bit adder Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 67

8 Reverse-Order simulation Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 68 Reverse-Order simulation cannot be used for sequential Circuits 101010101 100110011 011001100 010101010

9 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 69 5.3: Modeling Circuits for Simulation n Modules, blocks or components described by n Input/output (I/O) function n Delays associated with I/O signals n Examples: binary adder, Boolean gates, FET, resistors and capacitors n Interconnects represent n ideal signal carriers, or n ideal electrical conductors n Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy. ( HDL (Verilog ), VHDL)

10 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 610 Modeling Levels and Type of simulaton Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Transistor technology data, connectivity, node capacitances Tech. Data, active/ passive component connectivity Signal values 0, 1 0, 1, X and Z 0, 1 and X Analog voltage Analog voltage, current Timing Clock boundary Zero-delay unit-delay, multiple- delay Zero-delay Fine-grain timing Continuous time Modeling level Function, behavior, RTL Logic Switch Timing Circuit Application Architectural and functional verification Logic verification and test Logic verification Timing verification Digital timing and analog circuit verification

11 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 611 Example: A Full-Adder HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e); a b c d e f HA FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); HA1 HA2 A B C D E F Sum Carry A2 O1 N1 O2

12 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 612 CaCa Logic Model of MOS Circuit CcCc CbCb V DD a b c pMOS FETs nMOS FETs C a, C b and C c are parasitic capacitances DcDc DaDa c a b D a and D b are interconnect or propagation delays D c is inertial delay of gate DbDb

13 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 613 Options for Inertial Delay (simulation of a NAND gate) b a c (CMOS) Time units 0 5 c (zero delay) c (unit delay) c (multiple delay) c (minmax delay) Inputs Logic simulation min =2, max =5 rise=5, fall=3 Transient region Unknown (X) X

14 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 614 Signal States n Two-states (0, 1) can be used for purely combinational logic with zero-delay. n Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. n Four-states (0, 1, X, Z) are essential for MOS devices. See example below. n Analog signals are used for exact timing of digital logic and for analog circuits. 0 0 Z (hold previous value)

15 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 615

16 4 WeekFault-Tolerant System Design16 Level of Simulation  Register-level, for systems modeled entirely in RTL or as an interconnection of components modeled in RTL  Functional-level, for systems modeled as an interconnection of primitive functional blocks  Gate-level simulation;  Transistor-level (we consider logic level and not circuit-level analog simulation)  Mixed-level simulation

17 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 617 True-Value Simulation Algorithms n Compiled-code simulation n Applicable to zero-delay combinational logic n Also used for cycle-accurate synchronous sequential circuits for logic verification n Efficient for highly active circuits, but inefficient for low-activity circuits n High-level (e.g., C language) models can be used n Event-driven simulation n Only gates or modules with input events are evaluated (event means a signal change) n Delays can be accurately simulated for timing verification n Efficient for low-activity circuits n Can be extended for fault simulation

18 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 618 Compiled-Code Algorithm n Step 1: Levelize combinational logic and encode in a compilable programming language n Step 2: Initialize internal state variables (flip- flops) n Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations) n Execute compiled code Report or save computed variables

19 4 WeekFault-Tolerant System Design19 Compiled Simulation  Delay can be modeled by Explicitly adding them to Software model

20 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 620

21 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 621

22 4 WeekFault-Tolerant System Design22 Example: A Full-Adder HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); OR: O1, (a, b), (d); NOT: N1, (c), (e); AND: A2, (d, e), (f); a b c d e f FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); HA1 HA2 A B C D E F Sum Carry A1A1 O1O1 A2A2 N1N1 o2o2

23 4 WeekFault-Tolerant System Design23 Asynchronous circuit simulation with compiled-code model

24 4 WeekFault-Tolerant System Design24 0 001 1 10 Correct model for compiled simulation Shows that a compiled simulator cannot deal with Races and hazards

25 4 WeekFault-Tolerant System Design25 Main flow of event-driven simulation

26 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 626 Event-Driven Algorithm (Example) 2 2 4 2 a =1 b =1 c =1 0 d = 0 e =1 f =0 g =1 Time, t 0 4 8 g t = 0 1 2 3 4 5 6 7 8 Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g Time stack

27 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 627 Time Wheel (Circular Stack) t=0 1 2 3 4 5 6 7 max Current time pointer Event link-list

28 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 628 Efficiency of Event- driven Simulator n Simulates events (value changes) only n Speed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change Large logic block without activity Steady 0 0 to 1 event Steady 0 (no event)

29 4 WeekFault-Tolerant System Design29 Delay Models  Delay modeling is a key element controlling the trade-off between the accuracy and the complexity of the simulation algorithm.  Delay Modeling for gates:

30 4 WeekFault-Tolerant System Design30

31 4 WeekFault-Tolerant System Design31 d dfdf drdr Transition- independent delay model d I =4 d I =2 d

32 4 WeekFault-Tolerant System Design32 Output Inertial Delay

33 4 WeekFault-Tolerant System Design33 Delay Modeling for Functional element

34 4 WeekFault-Tolerant System Design34 Wire delays Modeled by delay element

35 Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 635 Summary n Logic or true-value simulators are essential tools for design verification. n Verification vectors and expected responses are generated (often manually) from specifications. n A logic simulator can be implemented using either compiled-code or event-driven method. n Per vector complexity of a logic simulator is approximately linear in circuit size. n Modeling level determines the evaluation procedures used in the simulator.

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