1. 1 Run on 25. October

2. 2 Full-size DCD Price: at least 32 k€ Return: April 201  Less test possibilities Full-size chip Wire-bondable DCD Price: 6.75 k€ Return: Januar 2011  Not compatible with existing systems Full-length column Bump-bonded compatible DCD Price: 13.5 k€ Return: Januar 2011 Compatible with existing systems  Half-length column - Allows test at full speed - Compatible to existing adapter - Fast delivery - We can test long matrix - Reasonable cost - Doable in 3 weeks

3. 3 List of Changes Connect NWell of the diode to vdda (improves speed) Make the signal switch placed in front of the ADC larger (improves linearity) Connect feedback capacitor before the source follower (improves stability) Disconnect RefIn from RefNWell (prevents crosstalk from RefIn) Change signal- and current switches to PMOS LN or NMOS (relevant for radiation hardness) Add cascode to SubOut (improves linearity) Make resistor switch of the same type as the signal switch (improves linearity) Make the input protection diode bigger Make the maximal DAC and SubIn current larger (64uA dispersion) Make digital Vdda wider Add monitor possibility for the voltages Add multiplexer for the needle card tests Ass spare channels Monitor ADC outputs Transconductor-based TIA (improves linearity)

4. 4 October 25 vs. Januar 11 Q: Why do we need submission in October? A: We want to test the readout of a full-size DEPFET matrix at the full readout speed before the start of production (June 2011) But… We can test the full-size DEPFET matrix with the DCD2 and Manuel’s measurements have already demonstrated the readout at the full speed. Q: Why do we need to test the full-size DEPFET matrix at the maximal speed before we start the production at all. A: Because we want to check the capability of the DEPFET matrix for the readout in 20us. What if the matrix is too slow? Do we have any possibility to speed up the matrix? Yes, we have / No, we have not Why a submission in January would be better? We would not work (again) under pressure and the quality of the work would be better We could do additional measurements check the radiation hardness of the DCDB before the submission

5. 5 Fast readout of long DEPFET Setup with DCD2, Switcher3 and 256x1024 COCGSA PXD5 device Single sampling with 90ns row time, clear moved to end allows >20ns complete clear, still 30ns safety margin for settling Shown first in Prague, 2010, M.Koch 5

6. 6 Long matrix COCG SA, pixel noise distribution statistics for 384 pixels 5000 samples each includes all common mode, pickup mean noise ~0.9LSB @10.4MHz (96ns) Low bias of input stage possible noise is lower than expected from measurements with directly bonded capacitance  we have RC-line 6

7. 7 The bug vdda ddda_dig nwell Smaller thr. Problem: we don‘t see any dependence on the column position