1. UART Jin-Fu Li

2. 2 EE613 VLSI DesignNational Central University Introduction UART (modem)  Universal asynchronous receiver and transmitter Data format Host processor 1 Modem Host processor 2 Modem Serial Data Channel Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 Start Bit Stop Bit Parity Bit

3. 3 EE613 VLSI DesignNational Central University Block Diagram of a UART Receiver controller Transmitter controller To host processor Clock Generator 1 Serial in Byte ready T byte Load XMT Data reg Serial out Sys clock Rcv shtreg Rcv datareg XMT datareg XMT shfteg 1

4. 4 EE613 VLSI DesignNational Central University UART – Transmitter Byte ready T byte Load XMT Datareg Bit count State Clear Load XMT shtreg Start Next state Shift Transmitter data path controller Byte ready: asserted by the host processor to indicate that data bus has valid data Load XMT Datareg: asserting transfers data bus to the transmitter data storage register, XMT datareg T byte: asserting initiates transmission of a byte of data, along with the stop, start, and parity bits Bit count: counts bits in the word during transmission State : state of the transmitter controller state machine Load XMT shtreg: asserting loads the contents of XMT datareg into XMT shtreg Start: signals the start of transmission Shift: directs XMT shtreg to shift by one bit toward the LSB and backfill with stop bit (1) Clear : clears bit counter Next state: the next state of the state machine controlling the data path of the transmitter

5. 5 EE613 VLSI DesignNational Central University FSM State Diagram of Transmitter Idle waiting sending Byte ready==0 Byte ready==1 T byte==1 T byte==0 Bit count ==word size +1 Shift=1 Start=0 Start=1 Clear=1 Load XMT shtreg=1

6. 6 EE613 VLSI DesignNational Central University UART – Receiver Read not ready in Sample counter Bit counter State load Clr sample counter Inc sample counter Next state Shift Receiver data path controller Serial in error1 error2 Read not ready in: signals that the host is not ready to receive data Sample counter: counts the samples of a bit Bit counter: counts the bits that have been sampled State: state of the state machine controlling the data path of the receiver Clr sample counter: clear sample counter Clr bit counter: clear bit counter Shift: causes RCV shftreg to shift towards the LSB Load: causes RCV shftreg to transfer data to RCV datareg Error1: asserted if host is not ready to receive data after last bit has been sampled Error2: asserts if the stop-bit is missing Next state: next state of the state machine controlling the data path of the receiver

7. 7 EE613 VLSI DesignNational Central University FSM State Diagram of Receiver Idle starting receiving Serial in==1 Serial in==0 Sample counter==3 Inc sample counter=1 Clr sample counter=1 Clear=1 Load XMT shtreg=1 Serial in==1 Serial in==0 Sample counter 1=3 Inc sample counter=1 Sample counter 1=word size -1