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Trap Engineering for device design and reliability modeling in memory/logic application 1/12 2015 년 02 월 xx 일 School of EE, Seoul National University 대표.

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Presentation on theme: "Trap Engineering for device design and reliability modeling in memory/logic application 1/12 2015 년 02 월 xx 일 School of EE, Seoul National University 대표."— Presentation transcript:

1 Trap Engineering for device design and reliability modeling in memory/logic application 1/12 2015 년 02 월 xx 일 School of EE, Seoul National University 대표 학생이승만 과제 책임자박영준 교수

2 연구 성과 요약 (’10.07~’14. 12) 1. 참여 기간 : 2010. 07. 01 ~ 현재 2. 전략산학 장학생 현황 : ( 총 0 명 ) - 1 차년도 이후 누적 입사 : 총 4 명 ( 입사 : 우준명, 박수영, 심경석, 최연규 ) - 학술연수 : 총 8 명 ( 졸업 : 이석하, 권혁제, 박상용, 권주성, 심혜원 / 김희중, 문중수, 김강욱 ) 3. 대표 연구 주제 : - 3D MCRD framework 을 통한 NBTI-SILC-TDDB simulation - BEOL TDDB 에 대한 Theoretical approach (MC / analytic method) - Billions of transistors 에 대한 소자 산포 예측, tail part modeling 4.5 년간 전략산학 연구 성과 결산 2/12

3 3/12 대표 논문 Review 논문 제목 : A 3-D Statistical Simulation Study of Mobility Fluctuations in MOSFET Induced by Discrete Trapped Charges in SiO2 Layer 논문 내용 : - Discrete trap 이 mobility 및 channel 의 current flux 에 미치는 영 향을 분석하였다. Si bar 에 대한 atomistic 한 시뮬레이션을 통해 트랩 주변으로 흐르는 current contour 가 mobility degradation 에 직접적인 영향을 준다는 것을 보였다.

4 선정 이유 : - Discrete trap 이 mobility 및 channel 의 current flux 에 미치는 영향을 분석하 였음. 이러한 현상은 scale down 된 소자의 trap 에 의한 신뢰성 분석에 필수적 이며 본 연구 과제의 주된 방법론임. 4/12 대표 논문 Review 저널 정보 : - 저널명 : IEEE Transactions on Nanotechnology -IF: 1.619, SJR 6175/29385 -Published 4 SCI Journal papers, 13 conference papers

5 Introduction 5 Status/Steps : Development of 3D MCRD Simulation Framework 1) Achievements: Unified Oxide Reliability Modeling Framework Interface reaction Molecular transport: Brownian random motion Conversion from precursor to active trap Leakage: Trap Assisted Tunneling current Breakdown: percolation model  Based on stochastic MC particle simulation 2) Predicting ‘tail’ part of 1 Billion transistors regarding step 1). percolation approach Oxide trap + discrete dopant  dV t distribution of 1Billion transistors in tractable time and resources - Solving present issues of ‘Causes’ and ‘Effects’ of degradation NBTI relaxation Unified model of NBTI-SILC-TDDB BEOL oxide TDDB  Setting up for practical simulation Framework -> Trajectory of sample hydrogen in the oxide

6 Unified Model of NBTI-SILC-TDDB in Gate Oxide Modeling Strategy 6 [TDDB: Time Dependent Dielectric Breakdown] [NBTI: Negative Bias Temperature Instability] cause [SILC: Stress Induced Leakage Current] > Gbit cells? effects Oxide Trap Profile BEOL oxide TDDB Apply percolation theory with MC method Field dependence based on percolation model Statistical Analysis Development of Analytical model

7 3/12 Need to predict.. After aging(NBTI,) - Trap(E,r) Time 0 - Random Dopant PDF VTVT VTVT Statistical approach to the reliability Goal for statistical analysis Finding rule for WC Verifying physical validity Probability of the WC

8 Worst case analysis (current blocking potential mountain chain) 7/12 TypeLWTox(SiO2)N-Sub(N D ) PMOS50nm40nm2nm5e18/cm3 Identifying anomalous V T shift according to the trap(fixed charge) distribution V D = -0.05V uniformlyrandomlyVertically distributed 20 fixed charges – 1e12/cm2 40 fixed charges - 2e12/cm2 80 fixed charges - 4e12/cm2 Uniformly distributed Vertically distributed - Worst case randomly

9 Simulation results, finding rules of the worst case (vd-1.0 mesh 2A) (vd-0.05 mesh 2A) Dependence on the one slit with maximum distance Dependence on the average distance between fixed charges 20Vertical +60 random 40Vertical +40 random 0Vertical +80 random

10 Probability calculation Percolation(potential chain) Start line path_4 (xd) path_1 (xa) path_2 (xb) path_3 (xc) Probability of a trap in a Cell = trap density x area of a Cell SourceDrain Trap density Probability of the WC Occurrence 1e11/cm2 1.78E-58 1e12/cm2 1.10E-36 1e13/cm2 3.02E-11 -Probability of the trap existence in a cell : 1e-3 (=1e11/cm2*1e-14cm2) -Considered distance between traps : 1nm~2nm  When the probability of a cell becomes 1/1000, probability of the occurrence of the worst case approaches to 3/100 billion transistors Calculation of the WC occurrence probability(permutation) x_position Kind of percolation 06 18 26 sample) A cell

11 Physical Validity of the Critical Length for WC Gate Oxide Substrate Depletion layer Ref[1] Verifying Physical Validity of Critical Length Method (on going) -Calculate potential fluctuation and its effective area due to a single charge through Image charge method -Definitions of effective potential area -The potential used to describe the scattering center(=screened Coulomb potential) suggested by BROOKS, HERRING, and DINGLE -How to cut off effective region from a infinite coulomb potential? -> Partial wave method (low energy scattering) -> Born approximation method (high energy scattering) => How to apply in defining critical length of the worst case?!  Electric field of a point charge through three or more dielectrics,  Si-SiO2 interface in not a equipotential surface, edge of the depletion region is equipotential ( symmetry to depletion edge) [1]T Takashima an, R Ishibashi, IEEE Trans. Electr. Insul, Vol EI-13, No 1, February 1978 [2] Brooks H., Vol. 7. Academic Press, Inc., New York (1956). [3] CONWELL E. M and WEISSKOPF V. F. “Theory of impurity Scattering in Semiconductors” Phys. Rev. 77, 388 (1950). Ref[2,3]

12 향후 계획 5 차년도 하반기 (’15.1~’15.6) 주요 연구 계획 -BEOL oxide TDDB Development of analytic model -‘tail’ part modeling of ‘over 1B’ devices Defining critical length and verifying Physical validity Comparing V T distribution tail of the conventional analytic model with modeling results Considering the quantum effect(DG) 12/12


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