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Copyright 2012, AgrawalLecture 12: Alternate Test1 VLSI Testing Lecture 12: Alternate Test Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical.

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Presentation on theme: "Copyright 2012, AgrawalLecture 12: Alternate Test1 VLSI Testing Lecture 12: Alternate Test Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical."— Presentation transcript:

1 Copyright 2012, AgrawalLecture 12: Alternate Test1 VLSI Testing Lecture 12: Alternate Test Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical and Computer Engineering Auburn University, Alabama 36849, USA vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal IIT Delhi, July 30, 2012, 4:00-5:00PM

2 Copyright 2012, AgrawalLecture 12: Alternate Test2 Contents  Setting thresholds in model-based test  Alternate test  Summary  References

3 Setting Thresholds in Model-Based Test  In model-based test, component values are determined.  Preset “thresholds” for component variation classify the device under test as good or faulty.  How do we determine the “thresholds”?  For example,  Circuit is good if R1’ ≤ R1 ≤ R1’’ Copyright 2012, AgrawalLecture 12: Alternate Test3

4 An Operational Amplifier Copyright 2012, AgrawalLecture 12: Alternate Test4 Gain = V2/V1 = R2/R1 V1 V2 R1 R2 +_+_

5 Pessimism in Model- Based Test Copyright 2012, AgrawalLecture 12: Alternate Test5 0 R1 R2 Only good devices accepted Yield loss Slope = G 0

6 Reducing Yield Loss Copyright 2012, AgrawalLecture 12: Alternate Test6 0R1 R2 Faulty devices accepted Reduced yield loss 0 Slope = G

7 Yield Loss and Defect Level  Yield loss: Amount of yield reduction because some good devices fail non-functional tests.  Defect level (DL): Fraction of faulty devices among those that pass non-functional tests.  Example: 1,0000 devices are fabricated. 7,000 are good. True yield, y = 0.7. Test passes 6,900 good and 150 bad devices. Then,  Yield loss = (7,000 – 6,900)/10,000 = 0.01 or 1%  DL = 150/(6,900+150) = 0.02128 or 2.128% or 21,280 DPM (defective parts per million) Copyright 2012, AgrawalLecture 12: Alternate Test7

8 Yield Loss and Defect Level Copyright 2012, AgrawalLecture 12: Alternate Test8 All fabricated devices Good devices Yield loss Defect level Devices passing test

9 Component Variation (Statistical) Copyright 2012, AgrawalLecture 12: Alternate Test9 Component (R or C) value Mean Component (R or C) value Mean UniformGaussian

10 Monte Carlo Simulation  Consider operational amplifier example.  R1 and R2 are random variables with given (uniform or Gaussian) probability density functions with  Mean = nominal value  Standard deviation based on manufacturing data  Generate large number of samples for R1 and R2  Simulate each sample using spice  Determine gain for each sample  For each set of tolerance limits, determine yield loss and defect level. Copyright 2012, AgrawalLecture 12: Alternate Test10

11 Monte Carlo Simulation Data Copyright 2012, AgrawalLecture 12: Alternate Test11 R1 0 R2 0 Slope = G

12 Setting Test Limits Copyright 2012, AgrawalLecture 12: Alternate Test12 0R1 R2 Minimize yield loss Minimize defect level 0 Slope = G

13 Alternate Test  Besides components (e.g., R1 and R2 for operational amplifier) easily measurable parameters used for testing.  An example is the supply current IDD of the operational amplifier.  A simple test is to measure IDD(0) for 0V input.  Monte Carlo simulation is then used to set the limits on IDD(0).  Large number of sample circuits with component variations are simulated to determine thresholds for IDD(0).  Additional measurements can improve test. Copyright 2012, AgrawalLecture 12: Alternate Test13

14 Alternate Test: Setting Thresholds Copyright 2012, AgrawalLecture 12: Alternate Test14 0 IDD(0) Gain Minimize yield loss Minimize defect level 0 Within spec. gain FailPassFail

15 References  P. N. Variyam, S. Cherubal and A. Chatterjee, “Prediction of Analog Performance Parameters Using Fast Transient Testing,” IEEE Trans. Computer-Aided Design, vol. 21, no. 3, pp. 349- 361, March 2002.  H.-G. Stratigopoulos and Y. Makris, “Error Moderation in Low-Cost Machine-Learning- Based Analog/RF Testing,” IEEE Trans. Computer-Aided Design, vol. 27, no. 2, pp. 339- 351, February 2008. Copyright 2012, AgrawalLecture 12: Alternate Test15

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