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Paper Review Yunsu Sung.

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Presentation on theme: "Paper Review Yunsu Sung."— Presentation transcript:

1 Paper Review Yunsu Sung

2 Contents Introduction Silicon photonics service PDK-Devices
Passive Modulator Detector System level design Integration Conclusion

3 Silicon photonics(SiP)
Matured infrastructure Complex integration Not far behind than other material system(Ex. InP)

4 System Design Requirement
Device standardization Process stability Key parameter variance of device is crucial Reliable device needed

5 Reliable device and low cost fabrication is needed!
Wafer Price 1 X Wafer 20 X Photomask 1 X $10000 Photomask Reliable device and low cost fabrication is needed!

6 Multi Project Wafer(MPW)
Sketch of MPW service Many user’s circuit integrate onto one wafer Able to design without fabrication ability Cost separate to several user First CMOS MPW service  MOSIS 8`` SOI wafer of IME die area

7 SiP platform MPW service

8 Foundry Offering Table of silicon photonics platform standard IME IMEC
IHP LETI Wafer 8inch SOI Si layer thick 220nm Buried Oxide 2μm Lithography 248nm 193nm Doping level 3(4p,3n) 3 2 MPW Price(/mm2) (PIC Active) SGD 1,145$/mm2 (48mm2) 1600 €/mm2 (6.25mm2) 2000 €/mm2 (1mm2) 1100 €/mm2 (passive + Heater) (6.29mm2) Characteristic Al Metal/Via Offer poly-si layer for grating 5level interconnects Unique Ti/TiN heater module ePIXfab provide MPW service of IMEC,IHP LETI.

9 Cross section of IME platform
Device library Cross section of IME platform Chip photo of IME Device Passive Modulator Detector

10 Eigenmode simulation of waveguide
Passive-Waveguide Eigenmode simulation of waveguide Waveguide structure Structure that guides optical waves Loss: ~2dB/cm

11 poly-si layer for grating
Passive-Grating Device to couple light on and off chip. Efficient chip testing IME IMEC IHP LETI Etch depth 60nm 50nm Insertion Loss 3.1dB 2dB 4.5dB Characteristic Non-uniform grating poly-si layer for grating Grating structure

12 Y-junction FDTD simulation
Passive-Y junction Y-junction structure Y-junction FDTD simulation 50:50 spliter, combiner Insertion loss: 0.28±0.02 dB

13 Passive-Waveguide crossing
Structure of waveguide crossing FDTD simulation Device to make easier routing for waveguide Insertion loss: 0.18±0.03dB Crosstalk -41±2dB

14 Passive-Directional Coupler
Structure of Directional coupler FDTD simulation Coupler to split or combine optical power Loss: 0.28±0.15dB Hard to calibrate

15 Modulator-MZM 3mm active length Vπ: 7V Insertion loss: 7dB
Extinction ration: 5.1dB 2.5V swing

16 Modulator-Ring Modulator
Device structure Characteristic curve EO response (BW 45GHz) Less power than MZI Bandwidth: 45GHz(Q,FSR: nm) Extinction ratio: 5dB 2.4V swing Insertion loss: 7dB

17 Detector-Ge pin PD Responsivity: 0.74±0.13 A/W
Device structure Responsivity: 0.74±0.13 A/W Dark current: 4±0.9μA(2V bias) Bandwidth: 30GHz IMEC PD: Responsivity:0.5A/W, Dark current:50nA, Bandwidth: 50Ghz

18 PDK Development PDK is still developing and more devices are adding
Diffent version of PDK PDK is still developing and more devices are adding Future capability 1310nm compatibility Polarization diversity

19 Photo of silicon chip package to polarization maintaining fiber
Packaging Photo of silicon chip package to polarization maintaining fiber Technology of enclosing or protect product for storage,sale and use Challenge Provide electrical/optical I/O Provide thermal interface Protect internal device

20 System Level Design Simulation and optimization are more important in system level Opsis Mentor Graphics Pyxis: Schematic capture and layout Calibre: DRC & LVS Lumerical: Interconnectoptical circuit simulation, Lumerical: FDTD,MODE,DEVICE photonic solver

21 Design for Manufacturability and Yield
Significant area for improvement More important in complex device design Unclear how the variation might affects a more complex system

22 Electronic-Photonic integration
Monolithic integration Sem photo of 90nm IBM chip Luxtera, IBM achieved No MPW service yet

23 Electronic-Photonic integration
2. Multi chip integration Advantage Decrease cost Can obtain better performance for each photonic and electronic device Three type of multi-chip integration Through silicon vias Flipchip bump bonging Wire bonding

24 Conclusion Silicon photonics will continues improvement
As a rate of device performance improvement slows complex system will be focus rather than device Process standarization and divece statistics will become more robust Development of design automation toll are very important

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