1.  Design of the Front end board is almost finished.  The PCB design has started with the block element.  Analog part of the design was checked by our Barcelona colleagues and bugs were fixed. ( Icecal pinout – Icecal to Adc link)  All schemas will be available soon on wiki or Calorimeter group web page.  Some “ details “has to be clarified  Power supplies on the backplane has to be define together with Youri for the LED calibration board  May we keep the + 5V or the – 5V or nor of them and use the power supply available to face the over power consumption  Power distribution schema has to be carefully checked.  Strategy in case of failure : over current on one part of the board …  Test of a modified power supply has to be done ( see with V Bobillier )  Is current limit fixed by both Feast or Max 869 is well adapted to protect the board in case of over current.  New power consumption should be compatible with the actual set of power supplies and cooling ( 2 * 50 A +5 ; 100 A +3,3V ; 50 A -5v; 50 A +5v)  50 W for the previous board, 70 W roughly estimated for the new version. June 26, 2016 1

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6. FormatDAQ LLT Bxid Bandwidth / Link Max Link number Assumptio n (link/Tell40 ) Fibre 196884,16E+0091,92E+00120 Fibre 296884,16E+0091,92E+00120 Fibre 396884,16E+0091,92E+00120 Fibre 496884,16E+0091,92E+00120 To reduce The costs The occupancy on the board The consumption It was agreed agreed have 4 fibres on each FEB Each fibre is operated in wide bus mode The corresponding bandwidth reduction leads to A splitting of the LLT data on 4 fibres Sending only 8 bits of the BX-id out of the 12 bits Each TELL40 can absorb ~80% (margin) of 100Gbit/s This leads to a maximum of 20 fibres / TELL 40 with the present constraints