1. ATCA LLP CARRIER BLOCK DIAGRAMS LAST UPDATE 20/12/2006 ISOCRATE R.

2. 200Mhz Clock and SYNC distribution TCLK GTS CORE SEGMENT PLL SWITCH SYNC SYNC_RTN GTS_CLOCK VIRTEX4 FX100 MAIN FPGA SMB INSP VIRTEX4 LX25 DATA DISTRIBUTON MGT CLOCK SYSTEM CLOCK_ SYNC 200MHz FANOUT SWITCH MASTER 200MHz SWITCH SEGMENT PLL SWITCH SYNC SYNC_RTN GTS_CLOCK VIRTEX4 FX100 MAIN FPGA SMB INSP VIRTEX4 LX25 DATA DISTRIBUTON MGT CLOCK SYSTEM CLOCK_ SYNC 200MHz FANOUT SWITCH SLAVE 200MHz SWITCH

3. Bcast & Msg Handler 1/2 SERIALIZERS 8  1 8 FROM REMOTE (TCLK) GTS MEZZANINE MAIN FPGA Msg_str0 Msg_str1 B_cast_data (7 downto 0) B_cast_str0 B_cast_str1 LLP Status (7 downto 0) GTS Status (7 downto 0) Msg_data (7 downto 0) SEG/CORE MEZZANINE Msg_str0 Msg_str1 LLP Status (7 downto 0) Msg_data (7 downto 0) 8 8 SERIALIZERS 8  1 8 8 8 FROM REMOTE (TCLK) TO REMOTE (TCLK) FANOUT TO MAIN FPGA, LOCALS MEZZANINES, AND REMOTE MEZZANINES (TCLK) Concentrator TRG/BCT FPGA

4. GTS CORE SEGMENT TCLK PORT Serializers FPGA MAIN FPGA Bcast & Msg Handler 1/2 SEGMENT TCLK PORT Serializers FPGA MAIN FPGA

5. Trig_req (1 downto 0) Trig_val (1 downto 0) Lt_data (7 downto 0) Tv_data (7 downto 0) Lt_Strobe Tv_Strobe TRIGGER Handler (serial) Trig_Rej (1 downto 0) SERs / DESERs 8  1 8 FANOUT TO OTHERS DEST GTS MEZZANINE 8 8 CORE MEZZANINE Trig_req (1 downto 0) MAIN FPGA ?? (1 downto 0)

6. Trig_req (1 downto 0) Trig_val (1 downto 0) Lt_data (7 downto 0) Tv_data (7 downto 0) Lt_Strobe Tv_Strobe Trig_Rej (1 downto 0) SERs / DESERs 8  1 GTS MEZZANINE Trig_req (1 downto 0) B_cast_data (7 downto 0) B_cast_str0 B_cast_str1 GTS Status (7 downto 0) 44 lines SERs / DESERs 8  1 8 8 8 8 8 10pairs (20 lines) 44 lines 200 lines 8 8 8 8 8 44 lines CORE MEZZANINE Sync_rtn Sync TCLK 266 / 448 ~50% of LX25_FF668 4 lines Alignement BUS (3 lines) CMC #1CMC #2CMC #3CMC #4FX100 TRIGGER & BCAST Handler (parallel)

7. TRIGGER Handler 2/2 GTS CORE SEGMENT TCLK PORT SEGMENT TCLK PORT Serializers FPGA MAIN FPGA Serializers FPGA MAIN FPGA

8. Serializer Data_A (15 downto 0) Empty_A Data_Ready_A Data_Request_A Using 1 16 bit port : 128 words/event 256 bytes/event 6 channels  1536bytes 16bit bus @ 100MHz Need 7.68µs (20µs avaible @ 50KHz) Deserializer 8 pairs ; 16 I/O 1024x18 DPRAM 9bit 1536*4 = 6144 byte/Event 32bit bus @ 100MHz Need 15.36µs (20µs avaible @ 50KHz) Data readout engine Data_A (15 downto 0) Empty_A Data_Ready_A Data_Request_A X4 Mezzanines 32bit Serializer 1024x18 DPRAM Serializer 9bit

9. MGT Clocking Layout RocketIO 101 MUX RocketIO 102 MUX RocketIO 103 MUX RocketIO 105 MUX MGTclk M34/N34 MGTclk AP28/AP29 RocketIO 106 MUX RocketIO 109 MUX RocketIO 110 MUX RocketIO 112 MUX RocketIO 113 MUX MGTclk AP3/AP4 MGTclk J1/K1 RocketIO 114 MUX ATCA FABRIC CH1-CH2 ATCA FABRIC CH3-CH4 ATCA FABRIC CH5-CH6 ATCA FABRIC CH7-CH8 ATCA FABRIC CH9-CH10 ATCA FABRIC CH11-CH12 USER SFP TRANSCEIVER RTM PCI EXPRESS LANE0 RTM PCI EXPRESS LANE5 RTM PCI EXPRESS LANE1 RTM PCI EXPRESS LANE2 100  250MHz PCI Express JITTER ATTENUATOR 200MHz GTS Clock (**) The ATCA FABRIC channels are routed from CHANNEL1 to CHANNEL12 by switches (***) User SFP could be used as 1GEnet or PCIExpress DAQ without FABRIC RTM PCI EXPRESS LANE3 RTM PCI EXPRESS LANE4 ABAB ABAB ABAB ABAB ABAB ABAB ABAB ABAB ABAB ABAB INSPECTION PADS 100MHz GTS Clock OPTICAL SFP INSPECTION PADS LOCAL 100MHz (EPSON ) PHASE LOCKED

10. RocketIO TEST RocketIO TEST MGT105A MGT105B RocketIO TEST RocketIO TEST MGT106A MGT106B RocketIO TEST RocketIO TEST MGT109B MGT109A FABRIC CHANNEL12 FABRIC CHANNEL11 FABRIC CHANNEL10 FABRIC CHANNELL9 FABRIC CHANNELL8 FABRIC CHANNELL7 FABRIC CHANNELL6 FABRIC CHANNELL5 FABRIC CHANNELL4 FABRIC CHANNELL3 FABRIC CHANNELL2 FABRIC CHANNELL1 ZONE3 (RTM) PCI Express Lane 0 ZONE3 (RTM) PCI Express Lane 1 ZONE3 (RTM) PCI Express Lane 2 ZONE3 (RTM) PCI Express Lane 3 RocketIO MGT102A MGT101B MGT114B MGT113A MGT103A iSFP Cage (1GEthernet,PCI Espress,User …) Clock in Cage To clock management The ATCA FABRIC is a DUAL STAR. This means that CHANNELS 1 of slot from 3 to 14 are are routed on CHANNEL1 to CHANNEL12 on HUB1 and CHANNELS 2 of slot from 3 to 14 are are routed on CHANNEL1 to CHANNEL12 on HUB2 (*) These cnannel must be routed on LLP cards, the others Channels are needed only on central switch. (*) MGT Layout ZONE3 (RTM) PCI Express Lane 4 ZONE3 (RTM) PCI Express Lane 5 RocketIO MGT112A MGT110B 10Gb Crosspoint Switch 2.5Gb Buffer

11. PNPN PNPN AC VIAS AC VIAS P N P N AC P N P N VIAS PNPN PNPN AC VIAS AC MGT topology template P P N N N P P N MGT105 A MGT105 B FABRIC 12 FABRIC 11 FABRIC 10 FABRIC 9

12. PNPN PNPN AC VIAS AC VIAS P N P N AC P N P N VIAS PNPN PNPN AC VIAS AC MGT topology template P P N N N P P N MGT106 A MGT106 B FABRIC 5 FABRIC 6 FABRIC 7 FABRIC 8

13. PNPN PNPN AC VIAS AC VIAS P N P N AC P N P N VIAS PNPN PNPN AC VIAS AC MGT topology template P P N N N P P N MGT109 A MGT109 B FABRIC 4 FABRIC 3 FABRIC 2 FABRIC 1

14. P N P N P N P N PNPN VIAS PNPN AC VIAS PCI Express topology template MGT102 A MGT101 B MGT114 B MGT113 A AC P N P N P N P N PNPN VIAS PNPN AC VIAS AC LANE 1LANE 2 LANE 3 LANE 4

15. PCI Express topology template MGT112 A MGT110 B P N P N P N P N PNPNPNPN VIAS AC VIAS AC VIAS P N P N LANE 6LANE 5

16. ATCA Configuration and status Xc9500 pld TCK0 TMS0 TDI0 TDO0 TCK1 TMS1 TDI1 TDO1 TCK2 TMS2 TDI2 TDO2 TCK3 TMS3 TDI3 TDO3 TCK4 TMS4 TDI4 TDO4 TCK5 TMS5 TDI5 TDO5 TCK6 TMS6 TDI6 TDO6 TCK7 TMS7 TDI7 TDO7 TCK_CON TMS_CON TDI_CON TDO_CON TCK_PPC TMS_PPC TDI_PPC TDO_PPC RTM/PPC CONF[1..0] MEZZANINE 0 CONF[1..0] MEZZANINE 1 CONF[1..0] MEZZANINE 2 CONF[1..0] MEZZANINE 3 FPGA_INIT/PROGRAM MEZZANINE 0 FPGA_INIT/PROGRAM MEZZANINE 1 FPGA_INIT/PROGRAM MEZZANINE 2 FPGA_INIT/PROGRAM MEZZANINE 3 I2C_SCK I2C_SCL MEZZANINE 0 MEZZANINE 1 MEZZANINE 2 MEZZANINE 3 MAIN FPGA FPGA TRIGGER AUX_1 AUX_2 FPGA_INIT/PROGRAM TRG FPGA FPGA_INIT/PROGRAM MAIN FPGA SEL PROGRAM MEZZANINE 0 SEL PROGRAM MEZZANINE 1 SEL PROGRAM MEZZANINE 2 SEL PROGRAM MEZZANINE 3 SEL PROGRAM TRG FPGA SEL PROGRAM MAIN FPGA Connected to Main FPGA IOs Fo FPGAs Update By Ethernet Connector 2.5 IOs 3.3 IOs

17. PLD for Switch and Buffer Management LX15_FF348 14 Signals FABRIC RX FABRIC TX ENA_A EQ_A0 EQ_A1 OSW_A ODE_A ENA_B EQ_B0 EQ_B1 OSW_B ODE_B TXSELA TXSELB RXSELA RXSELB x6 10 Signals FABRIC RX FABRIC TX ENA_A EQ_A0 EQ_A1 OSW_A ODE_A ENA_B EQ_B0 EQ_B1 OSW_B ODE_B x4 104 Signals 10/100 Signals 10/204 I2C_SCK I2C_SCL

18. ATCA I2C Layout and addressing Mezzanine 1 Monitoring ADC Serial EEPROM Temp Sensor 1 Temp Sensor 2 Temp Sensor 3 Jtag Supervisor Main Fpga IPMB0 IPMB1 Address $00 SWITCHS Supervisor RTM Address $00

19. ATCA Power Supply Fusing Filtering Protection -48V DC Hot Swap ENABLE DC to DC Converter DC to DC Converter DC to DC Converter DC to DC Converter P3V3-5A 16.5W MEZZANINE 1 MEZZANINE 2 MEZZANINE 3 MEZZANINE 4 MAIN BOARD P3V3-7A 23.1W P3V3/P2V5 Linear Reg M48/P12 DC P12/P3V3 DC MAIN BOARD P2V5-7A 17.5W P12/P2V5 DC FPGAs CORE P1V2-7A 8.4W P12/P1V2 DC FPGA MGT P1V2-4A 4.8W P12/P1V2 DC P5V0/P2V5 Linear Reg P2V5-1.5A P5V0/P1V8 Linear Reg P1V8-0.5A PROMS VCCAUX Fpga 1 VCCAUX MGT P5V0/P2V5 Linear Reg P2V5-1.5AVCCAUX Fpga 2 P5V0/P1V2 Linear Reg P1V2-0.5A VTTTXs P5V0/P1V2 Linear Reg P1V2-0.5AVTTRXs MGT BUFFERSP1V8-6A 10.8W P12/P1V8 DC P12V-14.7A 176.7(160.6)W P3V3-5A 16.5W M48V-4.0A 194.4(176.7)W DC-DC Efficency is estimated at least 90% ATC210 (210W) P3V3_BOOT 4x POWER ONE YS12S10 55W 6x POWER ONE YS12S10 55W P12/P5V0 DC P5V0-6A 30W

20. FPGA0 Temp MAX1617A Address $18 FPGA0 Temp MAX1617A Address $19 FPGA0 Temp MAX1617A Address $4C FPGA1 (LX15) DCDC_GOOD_* (9 wires) FPGA0 (FX100) FPGA2 (LX25)C iSFP ctrl (16 wires) Zarlink ctrl (9 wires) CLK PLL & switch ctrl (10 wires) ADC ctrl (9 wires) JTAG tap (4 wires) MAIN DCDC ctrl (7 wires) IPMI addr (7 wires) CMC1 Address $50 CMC2 Address $51 CMC3 Address $52 CMC4 Address $53 Address $54 I2C Temp sensors (3 wires) I2C Mezzanines (2 wires) JTAG Switch JTAG I2C Alarm & Warning (4 wires) Temp Sens MAX6626 Address $48 Temp Sens MAX6626 Address $49 Temp Sens MAX6626 Address $4A Temp Sens MAX6626 Address $4B ZONE 1 connector IPMI A and B (4 wires) IPMI A and B repeated (4 wires) RS232 Switch MAN SW MAN SW

22. FPGA0 Temp MAX1617A Address $18 FPGA1 Temp MAX1617A Address $19 FPGA2 Temp MAX1617A Address $4C CMC1 Address $50 CMC2 Address $51 CMC3 Address $52 CMC4 Address $53 Temp Sens MAX6626 Address $48 Temp Sens MAX6626 Address $49 Temp Sens MAX6626 Address $4A SFP Lanes I2C Multiplexer MAIN FPGA (FX100) SFP Clock Temp Sens MAX6626 Address $4B Prim. DC-DC ATC210 Address ? Mon. ADC ? Address ? IO Expander ? Address ? FPGA SW LX15 Address ? FPGA Ser. LX25 Address ? JTAG mgm XC95xx Address ? 1K EEPROM ? Address ?