1. 3 Dec, 2013 IFIC (CSIC – Universidad de Valencia) CLB: Current status and development

2. l CLBV2 PROTOYPES 25 FPGAs will be order The first protoypes are foreseen for 17 of December. (Valencia) The protoypes will be produced using lead: Higher quality To avoid whiskers 2

3. l 2nd LM32 INTEGRATION (FIRMWARE) TDC, AES, State Machine UART, GPIO, 3XI2C, SPI integrated all together New “Multiboot” slave in 0x0000C00 New “Start Time Slice UTC” slave in in 0x0000D00 Based on https://isvn.ific.uv.es/repos/KM3NeT/CLBv2/trunk/fw/CLBv2_Design/lm32_2nd 3

4. l 2nd LM32 INTEGRATION (FIRMWARE) Registers proposal is updated in googledocs 4 more addresses are needed for 2xI2C ports, Nanobeacon and Watchdog slaves Should we increase the secondary crossbar? 4

5. l 5 2nd LM32 INTEGRATION (FIRMWARE) Changes LM32_2n_pkg.vhd stmach_pkg.vhd aes_pkg.vhd tdc_pkg.vhd xwb_aes xwb_tdc xwb_stmach New: tslice_pkg.vhd i_aes i_tdc i_time slice i_state machine I will comment with Peter offline with more details to be synchronized with EASE tool Foreseen: Watchdog Nanobeacon

6. l 6 2nd LM32 INTEGRATION (FIRMWARE) Whisbone slaves codes are stored in: SVN: \trunk\fw\CLBv2_Design\lm32_2nd\modules\wishbone -wb_aes -wb_tdc -wb_stmach -wb_mboot Whole project is stored in: SVN: CLBv2\trunk\fw\TestDesigns\test_tdc_hydro_stmach

7. l 7 2nd LM32 INTEGRATION (SOFTWARE) Shell commands, drivers and libraries for wishbone slaves implemented and included in: SVN: CLBv2\trunk\sw\embedded\TestDesigns\test_tdc_hydro_stmach TDC: Core ON/OFF Channels OF/OFF Multiboot Multiboot Address trigger ON State Machine DOM id nº bytes of time slice Run number Start Time Slice Duration in ms or us

8. Fifo 31 TDCs TDC0 Management & Control 31 PMTs ADC Management & Control Hydrophone Fifo TDC 30 Fifo WB Crossbar (1x8) M M M M M S M M M M S State Machine l STATE MACHINE: TEST TDC MEMORY Debug RS232 UART S M JAVA APLICATION (GENOVA) 8 HYDRO MEMORY TDC AES Rx_mac2buf RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select Pause Frame S Management & Control

9. THANKS FOR YOUR ATTENTION!

10. FIRMWARE OVERVIEW Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x8) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S M M State Machine SPI S M Flash Multiboot Management & Control M S S 10