1. INTRODUCTION Microchip is the Embedded Control Solutions Company. The company’s focus is on products that meet the needs of the embedded control market. 8-bit General Purpose Microcontrollers (PICmicro™ MCUs)

2. PICmicro devices are grouped by the size of their Instruction Word. The three current PICmicro families are: 12-bit 1. Base-Line: 12-bit Instruction Word length 14-bit 2. Mid-Range: 14-bit Instruction Word length 16-bit 3. High-End: 16-bit Instruction Word length

3. Device Structure C O R E Perepherials Special Features

4. 1.Device Oscillator Revision 2.Reset logic Revision 3. CPU (Central Processing Unit) operation Revision 4. ALU (Arithmetic Logical Unit) operation Revision 5. Device memory map organization Revision 6. Interrupt operation Revision 7. Instruction set COR E

5. 1. General purpose I/O Revision 2. Timer0 Revision 3. Timer1 Revision 4. Timer2 Revision 5. Capture, Compare, and PWM (CCP) Revision 6. Synchronous Serial Port (SSP) Revision Perepherials

6. 7. USART Revision 8. Voltage References Revision 9. Comparators Revision 10. 10-bit Analog to Digital (A/D) Revision 11. Liquid Crystal Display (LCD) Drivers Revision 12. Parallel Slave Port (PSP) Perepherials

7. 1.Device Configuration bits Revision 2.On-chip Power-on Reset (POR) Revision 3. Brown-out Reset (BOR) logic Revision 4. Watchdog Timer Revision 5. Low power mode (Sleep) Revision 6. Internal RC device oscillator Special Features

8. Development Support 1.Code generation MPASM MPASM MPLAB-C MPLAB-C MP-DriveWay™ MP-DriveWay™ Hi-Tech Pic C compilerHi-Tech Pic C compiler 2. Software debug PICMASTER® In-Circuit Emulator PICMASTER® In-Circuit Emulator ICEPIC In-Circuit Emulator ICEPIC In-Circuit Emulator MPLAB-SIM Software Simulator MPLAB-SIM Software Simulator MPLAB ICD 2MPLAB ICD 2 3. Product evaluation boards EduPicEduPic

9. ARCHITECTURE The high performance of the PICmicro MCU family can be attributed to the following architectural features: Harvard architecture Harvard architecture Register file concept Register file concept All instructions single- word All instructions single- word LWI (Long Word Instruction) LWI (Long Word Instruction) Instruction pipelining Instruction pipelining Single-cycle instructions Single-cycle instructions Reduced instruction set Reduced instruction set Orthogonal instruction set Orthogonal instruction set

10. Harvard architecture Two separate memory Spaces for instructions and data. Increases throughputIncreases throughput Different program and data bus widths are possibleDifferent program and data bus widths are possible Fetches instructions and data from one memory. Limits Operating BandwidthLimits Operating Bandwidth

11. Instruction pipelining Allows overlap of fetch and execution.Allows overlap of fetch and execution. Makes single cycle execution.Makes single cycle execution. Program branches (e.g. GOTO, CALL or Write toProgram branches (e.g. GOTO, CALL or Write to PC) takes two cycles.PC) takes two cycles.

12. Block Diagram

13. Instruction Clock The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3, and Q4.

14. Instruction Fetch The four Q cycles that make up an instruction cycle (TCY) can be generalized as: Q1: Instruction Decode Cycle or forced No operation Q2: Instruction Read Data Cycle or No operation Q3: Process the Data Q4: Instruction Write Data Cycle or No operation

15. General Instruction Format Opcode d f (FILE#) 067813 Byte oriented file register operations Opcode f (FILE#) bit# 0291013 Bit-oriented file register operations Opcode k(literal) 07813 Literal and control operations Opcode k(literal) 0101113 CALL and GOTO instructions only The Mid-Range MCU instructions can be broken formats down into four general formats 3

16. FlashProgramMemory ProgramCounter 13 1 Level Stack 2 Level Stack 8 Level Stack... 13 InstructionRegister 14 InstructionDecod&Cont 8 To Data Mux Literal 7 To Addr Mux Byte & Bit Tcy Q1Q2Q3Q4

17. Data Process MUX InstructionRegister WRegister StatusRegister RAM FileRegisters 368 x 8 8 8 8 8 8

18. Memory DATA Memory 4 Banks4 Banks General Purpose RAM Special Function Registers (SFR) Program Memory 4 Pages4 Pages

19. Program Memory 13-bit program counter 13-bit program counter capable of addressing an 8K x 14 program memory space. This program memory space is divided into four pages of 2K words each Page 0 - 0000H-07FFH Page 1 - 0800H-0FFFH Page 2 - 1000H-17FFH Page 3 - 1800H-1FFFH

20. To jump between the program memory pages, the high bits of the Program Counter (PC) must be modified. This is done by writing the desired value into a SFR called PCLATH (ProgramCounter Latch High). 7766554433221100 ProgramCounter PCL PCH 4433221100776655PCLatch

21. (14 bits) PCH PCL 8 Level STACK

22. GOTO Instruction 078101112 PC 4433221100776655PCLatch FromOpcode 11 101099887766554433221100 3344 12121111 goto

23. CALL Instruction 078101112PC221100776655PCLatch3344 101099887766554433221100 12121111 Top os stack 13 FromIR 11 call

24. PC Relative Addressing (14-bit core) First write high byte to PCLATH.First write high byte to PCLATH. Next write low byte to PCL, this loads theNext write low byte to PCL, this loads the entire 13-bit value to PC. movlw HIGH Delay movwf PCLATH movlw LOW Delay movwf PCL movlw movwf

25. movf addwf retlw

26. Stack The stack space is not part of either program or data space and the stack pointer is not readable or writable. PUSH Operation Call instructionCall instruction Interrupt causes a branchInterrupt causes a branch POP Operation RETURN, RETLW or a RETFIE instruction execution. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

27. Example: Call of a Subroutine in Page1 from Page0 ORG 0x500 BSF PCLATH,8 BSF PCLATH,8 ; Select Page1 (800h-FFFh) CALL SUB1_P1 CALL SUB1_P1 ;Call subroutine in Page1 (800h-FFFh) : ; ORG 0x900 SUB1_P1: SUB1_P1: ; called subroutine Page1 (800h-FFFh) : ; RETURN RETURN ;return to Call subroutine in Page0 (000h-7FFh) ORG BSF pclatch

28. Data Memory Special Function Registers (SFR) Control the operation of the deviceControl the operation of the device General Purpose Registers (GPR) GPRs are the general area for data storageGPRs are the general area for data storage and scratch pad operations. GPRs are not initialized by a Power-on ResetGPRs are not initialized by a Power-on Reset and are unchanged on all other resets

30. status

31. Direct Addressing 7-bit direct address from the instruction 2-bits from STATUS register PR1:PR0 Byte&bit instruction Byte&bit instruction

32. Indirect Addressing 8-bit indirect address from the 8-bit indirect address from the FSR (File Select Register). FSR (File Select Register). 1-bit from STATUS register. 1-bit from STATUS register.

33. Example:Indirect Addressing Clear all RAM locations from 0x20 to 0x7F.Clear all RAM locations from 0x20 to 0x7F. Indirect address is loaded into FSR.Indirect address is loaded into FSR. Every time INDF is used as operand, registerEvery time INDF is used as operand, register pointed to by FSR is actually used. bcf STATUS,IRP bcf STATUS,IRP movlw 0x20 movlw 0x20 movwf FSR movwf FSR LOOP clrf INDF incf FSR,F incf FSR,F btfss FSR,7 btfss FSR,7 goto LOOP goto LOOP bcf clrf incf btfss

34. STATUS REGISTER Arithmetic status of the ALUArithmetic status of the ALU RESET statusRESET status Bank select bits for data memoryBank select bits for data memory Since the selection of the Data Memory banks is controlled by this register, it is required to be present in every bank. Also, this register is in the same relative position (offset) in each bank. RAM memory RAM memory

35. STATUS REGISTER IRPRP1 R\W IRP: Register Bank Select bit (used for indirect addressing) bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP1 R\WR\W bit 6:5 RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh)

36. TOPD R bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction R

37. ZDCC R/W bit2 bit2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result R/WR/W bit 0 C: Carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred

38. INTERRUPTS The PIC16F87XA family has up to 15 sources of interrupt. These sources generally include one interrupt source for each peripheral module, though some modules may generate multiple interrupts (such as the USART module)

39. INTCONRegister INTCONRegisterPIE/PIFRegisters

40. GIE bit is cleared to disable any further interruptGIE bit is cleared to disable any further interrupt The return address is pushed into the stackThe return address is pushed into the stack The PC is loaded with 0004h.The PC is loaded with 0004h. In the interrupt service routine the source(s)In the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. When an interrupt is responded to, next operation will executed:

41. Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit.The interrupts which were ignored are still pending to be serviced when the GIE bit is set again.

42. INTCON Register GIEPEIE R/W R/W bit 7 GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts ADDRESS (0Bh, 8Bh, 10Bh, 18Bh)

43. TOIETOIF bit 5 T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 2 T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow R/WR/W

44. bit 4 bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 1 bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred (must be cleared in software) 0 = The INT external interrupt did not occur INTEINTF R/W

45. bit 3 RBIE (1): RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 0 RBIF (1): RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state RBIERBIF R/W

46. PSPIE PIE1 Register PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt PSPIF: Parallel Slave Port Read/Write bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred PIR1 Register PSPIF

47. bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete ADIE PIE1 Register ADIF PIR1 Register bit 6 bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt

48. bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty RCIE PIE1 Register RCIF PIR1 Register bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt

49. bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full TXIE PIE1 Register TXIF PIR1 Register bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt

50. CCP1IE PIE1 Register bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt SSPIE bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt

51. CCP1IF PIR1 Register bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode.

52. SSPIF PIR1 Register bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The SSP interrupt condition has occurred and must be cleared in software before returning must be cleared in software before returning from the Interrupt Service Routine. from the Interrupt Service Routine.

53. The conditions that will set this bit are: SPI – A transmission/reception has taken place. SPI – A transmission/reception has taken place. I2C Slave – A transmission/reception has taken place. I2C Slave – A transmission/reception has taken place. I2C Master I2C Master - A transmission/reception has taken place. - The initiated Start condition was completed by the SSP module. - The initiated Stop condition was completed by the SSP module. - The initiated Restart condition was completed by the SSP module. - The initiated Acknowledge condition was completed by the SSP module. - A Start condition occurred while the SSP module was Idle (multi-master system). - A Stop condition occurred while the SSP module was Idle (multi-master system).

54. PIE1 Register TMR2IF PIR1 Register bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR2IE

55. PIE1 Register TMR1IF PIR1 Register bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow TMR1IE

56. PIE2 Register PIR2 Register bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disable the comparator interrupt -------- CMIE ------------------------ -------- CMIF ------------------------ CMIF: Comparator Interrupt Flag bit bit 6 CMIF: Comparator Interrupt Flag bit 1 = The comparator input has changed (must be cleared in software) 0 = The comparator input has not changed

57. PIE2 Register PIR2 Register ---------------- EEIE ---------------- bit 4 bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started bit 4 EEIE:EEPROM Write Operation Interrupt Enable bit 1 = Enable EEPROM write interrupt 0 = Disable EEPROM write interrupt ---------------- EEIF ----------------

58. PIE2 Register PIR2 Register ---------------- BCLIE ---------------- BCLIE: Bus Collision Interrupt Enable bit bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enable bus collision interrupt 0 = Disable bus collision interrupt ---------------- BCLIF ---------------- bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred in the SSP when configured for I2C Master mode 0 = No bus collision has occurred

59. PIE2 Register -------------------------------- CCP2IE CCP2IE: CCP2 Interrupt Enable bit bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt

60. PIR2 Register -------------------------------- CCP2IF bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused.

61. Context Saving During Interrupts 1. Stores the W register regardless of current bank. 2. Stores the STATUS register in Bank0. 3. Executes the Interrupt Service Routine (ISR) code. 4. Restores the STATUS (and bank select bit register). 5. Restores the W register. If additional locations need to be saved before executing the Interrupt Service Routine (ISR) code, they should be saved after the STATUS register is saved (step 2), and restored before the STATUS register is restored (step 4).

62. Saving the STATUS and W Registers in RAM MOVWF W_TEMP ; Copy W to a Temporary Register regardless of ;current bank SWAPF STATUS,W SWAPF STATUS,W ; Swap STATUS nibbles and place into W register MOVWF STATUS_TEMP MOVWF STATUS_TEMP ; Save STATUS to a Temporary register ; in Bank0 : : (Interrupt Service Routine (ISR) ) : SWAPF STATUS_TEMP,W SWAPF STATUS_TEMP,W ; Swap original STATUS register value ; into W (restores original bank) MOVWF STATUS MOVWF STATUS ; Restore STATUS register fromW register SWAPF W_TEMP,F SWAPF W_TEMP,F ; Swap W_Temp nibbles and return ; value to W_Temp SWAPF W_TEMP,W ; Swap W_Temp to W to restore original ; W value without affecting STATUS SWAPF

63. Initialization and Enabling of Interrupts ; This is the Interrupt Enable PIE1_MASK1 EQU B‘01101010’ ; This is the Interrupt Enable ; Register mask value : : : ; Bank0 CLRF STATUS ; Bank0 CLRF INTCON ; Disable interrupts and clear some flags CLRF PIR1 ; Clear all flag bits BSF STATUS, RP0 ; Bank1 MOVLW PIE1_MASK1 ; This is the initial masking for PIE1 MOVWF PIE1 BCF STATUS, RP0 BCF STATUS, RP0 ; Bank0 BSF INTCON, GIE BSF INTCON, GIE ; Enable Interrupts EQU REGISTERS