1. UniBoard Progress Meeting, December 2009 Jonathan Hargreaves, JIVE EVN Correlator Design UniBoard Progress Meeting, December 2009 Contract no. 227290

2. UniBoard Progress Meeting, December 2009 Basic Configuration FN 0 Station 0-7 2 Pol, 8 Bit, 64 MHz BW FN 1 Station 8-15 2 Pol, 8 Bit, 64 MHz BW FN 2 Station 16-23 2 Pol, 8 Bit, 64 MHz BW FN 3 Station 24-31 2 Pol, 8 Bit, 64 MHz BW BN 0 2112 corr products 16 MHz BW BN 1 2112 corr products 16 MHz BW BN 2 2112 corr products 16 MHz BW BN 3 2112 corr products 16 MHz BW Station Data in to 10GbE Ports Correlation Products out to backend computer Works with 800MT/s DDR3

3. UniBoard Progress Meeting, December 2009 Expanded Configuration FN 0 Station 0-7 2 Pol, 8 Bit, 128 MHz BW FN 1 Station 8-15 2 Pol, 8 Bit, 128 MHz BW FN 2 Station 16-23 2 Pol, 8 Bit, 128 MHz BW FN 3 Station 24-31 2 Pol, 8 Bit, 128 MHz BW BN 0 2112 corr products 32 MHz BW BN 1 2112 corr products 32 MHz BW BN 2 2112 corr products 32 MHz BW BN 3 2112 corr products 32 MHz BW Station Data in to 10GbE Ports Correlation Products out to backend computer May need 1333MT/s DDR3 4GB for FN

4. UniBoard Progress Meeting, December 2009 Band Modes For the basic configuration a UniBoard can be set up in one of 7 modes 64 x 1MHz bands 32 x 2MHz bands 16 x 4MHz bands 8 x 8MHz bands 4 x 16MHz bands 2 x 32MHz bands 1 x 64MHz band Mixed modes possible at cost of complexity Number of bands double in the expanded configuration

5. UniBoard Progress Meeting, December 2009 Spectral Line FN 0 Station 0-7 2 Pol, 8 Bit, 64 MHz BW FN 1 Station 8-15 2 Pol, 8 Bit, 64 MHz BW FN 2 Station 16-23 2 Pol, 8 Bit, 64 MHz BW FN 3 Station 24-31 2 Pol, 8 Bit, 64 MHz BW BN 0 2112 corr products 16 MHz BW BN 1 2112 corr products 16 MHz BW BN 2 2112 corr products 16 MHz BW BN 3 2112 corr products 16 MHz BW Station Data in to 10GbE Ports Correlation Products out to backend computer Subset of frequency points from each FN routed via spare 10GbE ports to another UniBoard

6. UniBoard Progress Meeting, December 2009 BN Overview MAC Engine F I F O Control Logic DDR3 Interface II DDR3 Interface I DDR3 Module II SEQUENCERSEQUENCER 1GbE PORT 10Gb E PORT Nios Embedded Processor F IFOF IFO REGISTERBANKREGISTERBANK F I F O INPUT BUFFERSINPUT BUFFERS OUTPUTBUFFEROUTPUTBUFFER

7. UniBoard Progress Meeting, December 2009 BN Correlation Engine 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 24 25 26 27 28 29 30 31 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 17 18 19 20 21 22 21 20 19 18 17 1623 24 25 26 27 28 29 30 31 31 30 29 28 27 26 25 24 a) b) c) 132 MAC cells clocked > 260MHz One half-DSP block plus 72 registers per MAC cell for 36 bit accumulation Sixteen passes: L-L, R-R, L-R, R-L

8. UniBoard Progress Meeting, December 2009 BN Resources Half DSP blocksSRAM (1000 bits) LC regs (1000’s) Input FIFO016 DDR3 Interfaces08515 DDR3-DSP FIFO01 MAC Input Buffers0554.6 Correlation Engine13209.5 MAC Output Buffers0304 Output FIFO016 Output port (10GbE)0224.2 Total132 (322)499 (14,283)33.3 (182.4) Plus: Control system, SOPC with Nios processor Validity – scale data path by 10/9, 2.1k LC regs + 34k storage to accumulate Test pattern generator

9. UniBoard Progress Meeting, December 2009 FN Overview course F I F O VDIF Header Control Logic DDR3 Interface I DDR3 Module I Read Addr Calc PFB 1GbE PORT FN-BN Serial Nios Embedded Processor FFT 10GbE PORT F I F O Delay Model Calc fine Complex mixer Phase Model Calc F I F O S Model updates FN-BN Serial Station mapping

10. UniBoard Progress Meeting, December 2009 FN Resources Half DSP blocksSRAM (1000 bits) FIFO Buffering02100 DDR3 interfaces043 Delay Model30614 Cplx mixers & PFB232304 FFT154608 Power measurement32 Normalization16 Output FIFO016 Total116 (322)9685 (14,283) Not including: SOPC, Validity, test OK for multipliers but on chip storage is critical – no room for expansion Need to offload some to DDR3

11. UniBoard Progress Meeting, December 2009 Timing Ten millisecond tick FN Header Control Logic Tick Generator Correlator Clock Station Data One Secon d Tick Nios Control Nios Control Nios Control Nios Control Correlator time set to approx half second later than stations Controller selects a master and 3 slaves Second tick and 10ms tick distributed via INTA, INTB lines to synchronize FNs Correlator time base runs slightly faster than real time Ticks adjusted as necessary to keep buffers stable