1. DAQ Selection Discussion DAQ Subgroup Phone Conference Christopher Crawford 2013-01-11 1

2. Reminder – from April DOE review Event / Data rate < 5000/s decay rate in active volume; 600/s protons in upper detector Coincident electron in adjacent pixel (7/127), either top or bottom detector Accidentals from decay products <1% for 40 us coincidence window PIXIE-16 waveform digitizer: 100 MHz sample rate, 12 bit ADC 14 pixels * 1 us * 100 MS/s * 12 bit * 5000 /s = 11 MB/s; 12 TB / 2 weeks Trigger scheme Trigger levels: 1) DIGITIZER threshold, 2) FPGA readout, 3) CPU storage Trigger separately on protons / electrons, form coincidences in software Energy sum trigger for adjacent pixels – detection of lower-threshold events Read out 6 neighboring pixels around trigger Local trigger decisions based on hit information from other modules: main FGPA hits PXI bus trigger lines digitizer FPGA fiber optics readout rear I/O module 2

3. Trigger options Levels: 1.Overthreshold in single pixel 2.Coordinated readout in FPGA 3.Validation in CPU before write to disk Data Rates: 14 pixels x 12 bits x 100MS/s Trigger Options: a)Independent e, p: 13 MB/s filter coincidence in CPU b)Proton trigger: 51 MB/s search for e in CPU (no advantage?) c)Electron trigger: 480 MB/ssearch for p in CPU (no advantage?) rate1 us40 us proton 600 Hz1.3 MB/s51 MB/s electron 5 kHz11 MB/s480 MB/s 3

4. Trigger options Multipixel clustering: a)Coordinated readout: easier/important for offline energy construction b)Energy sum trigger: harder/relevant? low energy protons in 1 pixel 1.Coincidence of multiple hits in L2 trigger logic – doesn’t require trap. filter 2.Query total energy from neighbors of single hit – higher efficiency c)Low threshold trigger: average signal before discrimination 4 Multiple thresholdsSingle threshold

5. XIA system $280k including spare digitizer module; price break on RTM Good support: FPGA & optical Rear Transition Module development 250 MHz, 14 bit fADC; excellent energy reconstruction algorithms 5

6. XIA custom firmware Overlapping pileup trigger –Record back-to-back events Multichannel readout –Each pixel broadcasts threshold and pixel # –Each module decides which pixels to readout according to lookup table Energy sum (cluster) trigger –3 separate thresholds (2 bits) broadcast with pixel # –Lookup table extended for all combinations of pixel/threshold –Alternative: single-threshold cluster based on full energy information a) hit broadcasts energy b) neighbors broadcast energy c) discriminate on sum Trigger distribution bus –38 global + 52 half crate + 21 nearest neighbor lines –Note: enough lines to broadcast 4 pixel# + 8 energy bits per module (more if we only do cluster trigger for pixels in fiducial volume) could even discriminate on sum of 8-bit energies 6

7. NI system $300k, (discounted from $850k) All communications on fiber PCIe bus - FAST Different digitizer architecture: –16 bit, 120 MHz –data is continuously written to single 512 MB ring buffer –CPU can request any ranges of data within the last 0.5 s Convenience of programming: –Level 1 trigger is implemented in FPGA, written in LabVIEW we could include trapezoid filters to calculate the energy sum –Level 2/3 triggers implemented in CPU easy to implement powerful global triggers fast communication via DMA over PCIe bus Could implement energy sum trigger by adding up total energy –Low-threshold pixel prompts reading energy of all neighbors –Level 2 trigger on energy sum –Lossless for a threshold of E 0 /n assuming n-pixel events 7

8. NI architecture 8

9. Jlab system Based on custom hardware for 12 GeV upgrade: $128 total a.2*$9k VXS crate (VME 2eSST + serial fabric on J0 with a double-star topology to two switchboards) (page 5) b.2*$6k single-board computer (SBC) which runs entire DAQ software, writes out to RAID c.2*$5k crate trigger processor (CTP) with VirtexV FX70T, 5 Gbps to fADCs, 8 Gbps fiber to other crate (pate 21) d.2*8*$5k 16-ch 250 MHz, 12 bit fADC digitizers with 2eSST readout, but only 4x 4 us ring buffer (page 23) High-speed connection (50 bits/cycle) from each module to CTP –Could implement powerful global trigger in FPGA We have to develop entire firmware and software ourselves –Would cost $100k for engineer for 1 year, uncertain schedule 9

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11. CAEN system $260k not including optical links between detectors External FPGAs connected to modules by ribbon cable We would have to develop global trigger logic, and design optical link between crates 11