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Trigger & DAQ Ole Hansen SBS Collaboration Meeting 19 March 2010.

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Presentation on theme: "Trigger & DAQ Ole Hansen SBS Collaboration Meeting 19 March 2010."— Presentation transcript:

1 Trigger & DAQ Ole Hansen SBS Collaboration Meeting 19 March 2010

2 GEp(5) Trigger Considerations Very high luminosity, L 8x10 38 cm -2 s -1 Very high luminosity, L 8x10 38 cm -2 s -1 Open detectors, large solid angle Open detectors, large solid angle Challenges Challenges: Trigger setup: Trigger setup: Trigger on calorimeter hits Trigger on calorimeter hits High calorimeter thresholds High calorimeter thresholds Coincidence of e-p angular correlations Coincidence of e-p angular correlations H(e,ep) elastic

3 GEp(5) Calorimeter Rates HCALECAL Electron rate estimate w/2.5 GeV threshold (85% of E elas ): 60 kHz (CDR section 5.1.7) Hadron rate estimate using SLAC & DESY data, Wiser code: w/4.5 GeV threshold: 1.5 MHz Background rate vs. cut on deposited energy (MC studies in progress) 5 kHz coincidence rate w/ 50 ns window 5 kHz coincidence rate w/ 50 ns window NB: Good resolution 8%/ E 8%/ E

4 e-p Kinematic Correlation 10 x 20 HCAL blocks 20 x 76 ECAL blocks (CDR section F.3)

5 Calorimeter Sums 10 x 20 HCAL blocks 20 x 76 ECAL blocks (CDR section F.3) sum-32 4x37 = 148 sum-32 7x17 = 119 sum-16 sum-16

6 Calorimeter Sectioning HCAL sums of 16: 7x17 = 119 ECAL sums of 32: 4x37 = 148 (CDR section F.3) 7x7 4x10 4x9

7 Calorimeter Sectioning HCAL sums of 16: 7x17 = 119 ECAL sums of 32: 4x37 = 148 (CDR section F.3) Rate reduction: x5 correlate (40)

8 ECAL Sums x5 sum-8 to ADCs 3333 to other Electronics exists (used with BigCal in Hall C) 148 x sum-32

9 HCAL Sums 12-bit pipelined FADCs CPUCPU TITI SMARTTRIGSMARTTRIG x16 x8 x200 16x8 bits/16 ns = 8 Gb/s per FADC (!) x(7x7) = 196 sum-16 logic signals x196

10 SMART Trigger Module VME Deserializer 13 x 8 Gb/s 2 kB SRAM FIFO FPGA 64 x 8-bit sums & discriminators VERY PRELIMINARY FPGA 64 x 8-bit sums & discriminators Digital Out to coinc. FPGAs Fan-out 192 est. processing time ns

11 L2 Coincidence Logic For each calorimeter section (4x): CAEN 1495 FPGA VME module (160 inputs) 50 ns latency VME 36 (40) x ECAL sum-32 Smart HCAL sum, 1 µs latency 49 x HCAL sum-16 To L2 trigger OR 1 µs variable delay L1 trigger

12 Two-Level Trigger Level 1 Level 1 –100 ns latency –Generated by electron arm (60 kHz rate) –Gate for Fastbus & non-pipelined VME Level 2 Level 2 –Assume up to 1 μs latency –FPGA-based coincidence logic –1 kHz physics rate –Fast Clear FB & VME after L2 timeout < 10% DT

13 DAQ Requirements Data rate driven by Trackers: (assuming 2 bytes/channel – 7 bits address, 9 bits data) Data rate driven by Trackers: (assuming 2 bytes/channel – 7 bits address, 9 bits data) Other detectors, contingency, … design for 100 MB/s data rate Other detectors, contingency, … design for 100 MB/s data rate

14 12 GeV Upgrade Electronics Under development by JLab DAQ group Under development by JLab DAQ group Fully pipelined Fully pipelined 200 kHz L1 trigger rate capability 200 kHz L1 trigger rate capability Synchronous trigger distribution, 250 MHz ref. clock Synchronous trigger distribution, 250 MHz ref. clock VME64x front-end crates with support for VME64x front-end crates with support for –High-speed readout modes (2eVME, 2eSST) up to 200 MB/s –On-module event buffering - up to 200 events –Gigabit uplinks to event builder CODA 3 software CODA 3 software Will use some of this technology + custom modules Will use some of this technology + custom modules

15 Future Front Ends (graphics from Dave Abbott) Trigger Interface (TI) CODA 2 & 3 support FADCF1TDC CPU: Intel or Motorola Linux or vxWorks Dual GigE >200 MB/s CODA 2 & 3 ROC Clock/Trigger Signal Distribution (SD) Crate Trigger Processor (CTP) (optional) VME64x/VXS Crate Trigger & Clock (via fiber) Data (via Gigabit Ethernet)

16 Hall A Data Path ROC Gigabit Switch ADAQL Event Builder 1x (or 2x) GigE

17 Trigger & DAQ Responsibilities New Hampshire New Hampshire –ECAL analog calorimeter summing logic Rutgers Rutgers –CAEN v1495 coincidence logic INFN Rome & Genova INFN Rome & Genova –GEM readout electronics & DAQ interface Jefferson Lab Jefferson Lab –HCAL digital summing electronics –DAQ setup Norfolk State Norfolk State –2 nd and 3 rd tracker front-end electronics

18 Near-Term Plans Test 10x10 cm 2 GEMs during PREX (spring 2010) Test 10x10 cm 2 GEMs during PREX (spring 2010) GEM VME readout prototypes expected ready in spring or summer 2010 (maybe for PREX) GEM VME readout prototypes expected ready in spring or summer 2010 (maybe for PREX) Ongoing tests & prototyping with CAEN v1495 FPGAs at Rutgers Ongoing tests & prototyping with CAEN v1495 FPGAs at Rutgers v1495 radiation hardness test during PREX v1495 radiation hardness test during PREX

19 CAEN 1495 FPGA Prototyping (Rutgers) Have 3 v1495s for Fermilab E906 Have 3 v1495s for Fermilab E906 Programming & testing of E906 trigger conditions (256 inputs) in progress Programming & testing of E906 trigger conditions (256 inputs) in progress Gaining experience with hardware and software Gaining experience with hardware and software

20 Summary GEp(5) Trigger requires some R&D GEp(5) Trigger requires some R&D –Digital summing logic for HCAL –FPGA coincidence logic Data Acquisition fairly challenging, but doable Data Acquisition fairly challenging, but doable –100 MB/s data up to 5 kHz trigger rate –12 GeV DAQ architecture, CODA 3 –Pipelined electronics –Custom modules First prototyping & testing underway First prototyping & testing underway


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