GlueX Level-1 trigger group responsibilities are to commission the trigger electronics and provide tools for monitoring the trigger performance. Main tools: Test Vector Trigger monitors Test Vector: Hard ware check out: Check performance of the electronic boards at system level (synchronization, drift, glitch … ). Will be performed during the trigger commissioning phase and before taking the data. Implementation: Write predefined signal shapes to the FADC250 ’ s FPGA memory. Run the trigger hardware. Verify the trigger algorithm Compare hardware output with the MC predictions. Trigger Monitors: Perform online monitoring of the trigger rates, occupancies, … during data taking Will be implemented as scalers residing inside FPGAs. Level 1 Trigger Commissioning, Trigger Work Shop, July 8, 2010 2 Trigger Commissioning and Monitoring Tools
Checking Hardware X1 + X2 Module or system 1101 1000 … 1100 1001 … 11001 10001 … Compare Test Vector Loaded through VME 11001 10001 … Expected Results Pass /Fail= pass != Fail Failed Patterns ; Expected Results X1 X2 Concept applies at module or system level Level 1 Trigger Commissioning, Trigger Work Shop, July 8, 2010 3
L1 Trigger Play Back Input Data Memory 1 1101 1000 … Memory 2 1100 1001 … X1 X2 PlayBack 1100 1001 … 1101 1000 … Level 1 Trigger Commissioning Trigger Work Shop, July 8, 2010 4 Test Vector Loaded through VME
Front End Crate 1 GLOBAL CRATE TS CRATE System Check Out and Debugging Using PlayBack Front End Crate N FADC250 Ch16 ROC FADC250 Ch1 CTP ROC TI SD SSP 1 SSP N GTP TS TD ROC SD CTP ROC FADC250 Ch1 FADC250 Ch16 SD TI TRIG1 TA TRIG1 FIBER 5 TA FIBER VXS PB : Firmware Play Back Test Vector TA : Firmware Test Algorithm. Can be processing algorithm PBTA PBTA TRIG2 PBTA PBTA TRIG2 VXS TR VME TR VME Ethernet MONITOR Crate Board Register FailedPattern ExpPattern SERVER TR : Software Test Routine.
Where to Input PlayBack (Test Data) in FADC250 Board Placing PlayBack at Xilinx VLX110 FPGA on the FADC250V2 allows test data to propagate to rest of system. CH1 CH16 Serial GigBits to CTP VME to ROC Lemo ADC1 IC ADC16 IC Xilinx VLX110 FGPA Xilinx FX70T FGPA FIFO FADC250V2 Data Path Level 1 Trigger Commissioning Trigger Work Shop, July 8, May 10, 2010 6
PlayBack Firmware in Xilinx VLX110 FPGA Memory 1 0 Test-On CH16-On To CH16 Processing 0 Test-On CH1-On To CH1 Processing Test-On Memory 16 Rising edge of Trig plays all data Trig ADC 16 Test Data ADC 1 Test Data Samples from ADC1 IC Samples from ADC16 IC PlayBack (Trig2) Test Data from VME Test-On and CHx_On are Configuration bits from VME Each memory can hold 32 test data points @250Mhz Clock, each memory provides 128nS of play back. Data at memory location 0 is the pedestal Level 1 Trigger Commissioning, Trigger Work Shop, July 8, 2010 7