1. 1 CS/COE0447 Computer Organization & Assembly Language Logic Design Appendix C

2. 2 Outline Example to begin: let’s implement a MUX Gates, Truth Tables, and Logic Equations Combinatorial Logic Constructing an ALU Memory Elements: Flip-flops, Latches, and Registers

3. 3 Logic Gates Y=A&B Y=A|B Y=~(A&B) Y=~(A|B) 2-input AND 2-input OR 2-input NAND 2-input NOR A B A A A B B B Y Y Y Y

4. 4 Multiplexor If S then C=B else C = A A C B S 0 1 How many bits is S? 1, since it is choosing between 2 values Let’s see how to implement a 2-input MUX using gates. Hint: the answer uses AND gates, an OR gate, and one INVERTER Answer in lecture

5. 5 Computers and Logic Digital electronics operate with only two voltage levels of interest: high and low voltage. –All other voltage levels are temporary and occur while transitioning between values We’ll talk about them as signals that are –Logically true; 1; asserted –Logically false; 0, deasserted 0 and 1 are complements and inverses of each other

6. 6 Combinational vs. Sequential Logic Combinational logic –A function whose outputs depend only on the current input Sequential logic –Memory elements, i.e., state elements –Outputs are dependent on current input and current state –Next state is also dependent on current input and current state

7. 7 Combinational Logic inputsoutputs ……

8. 8 Sequential Logic inputsoutputs …… clock current state next state

9. 9 The next set of topics [until the sequential logic picture we just saw pops up again] will only be about combinatorial logic

10. 10 Functions Implemented Using Gates inputsoutputs …… ? Combinatorial logic blocks implement logical functions, mapping inputs to outputs

11. 11 Describing a Function Output A = F(Input 0, Input 1, …, Input N-1 ) Output B = F’(Input 0, Input 1, …, Input N-1 ) Output C = F’’(Input 0, Input 1, …, Input N-1 ) Methods –Truth table (since combinatorial logic has no memory, it can be completely specified by a truth table) –…[in a moment]

12. 12 Truth Table InputOutput ABC in SC out 00000 00110 01010 01101 10010 10101 11001 11111

13. 13 Truth Tables In a truth table, there is one row for every possible combination of values of the inputs Specifically, if there are N inputs, the possible combinations are the binary numbers 0 through 2EN - 1. For example: –3 bits (0-7): 000 through 111 –4 bits (0-15): 0000 through 1111 –5 bits (0-31): 00000 through 11111 While we could always use a truth table, they quickly grow in size and become hard to understand and work with Boolean logic equations are more succinct

14. 14 Describing a Function Output A = F(Input 0, Input 1, …, Input N-1 ) Output B = F’(Input 0, Input 1, …, Input N-1 ) Output C = F’’(Input 0, Input 1, …, Input N-1 ) Methods –Truth table –Boolean logic equations Sum of products Products of sums

15. 15 Truth Table and Equations S = A’B’C in +A’BC in ’+AB’C in ’+ABC in C out = A’BC in +AB’C in +ABC in ’+ABC in InputOutput ABC in SC out 00000 00110 01010 01101 10010 10101 11001 11111 Each output has its own…? Column in the truth table And its own Boolean equation

16. 16 Truth Tables and Equations All functions specified by truth tables can also be specified by Boolean formulas [and vice versa] So, let’s look more closely at Boolean algebra

17. 17 Boolean Algebra Boole, George (1815~1864): mathematician and philosopher; inventor of Boolean Algebra, the basis of all computer arithmetic Binary values: 0, 1 Two binary operations: AND (  /  ), OR (  ) –AND is also called the logical product since its result is 1 only if both operands are 1 –OR is also called the logical sum since its result is 1 if either operand is 1 One unary operation: NOT (~)

18. 18 Laws of Boolean Algebra Identity, Zero, and One laws –a  a = a+a = a –a  1 =a; a+0 = a [“copy” operations] –a  0 =0; a+1 = 1 [deassert by ANDing with 0; assert by ORing with 1] Inverse –a  a = 0; a+a = 1 Commutative –a  b = b  a –a+b = b+a Associative –a  (b  c) = (a  b)  c –a+(b+c) = (a+b)+c Distributive –a  (b+c) = a  b + a  c –a+(b  c) = (a+b)  (a+c)

19. 19 Laws of Boolean Algebra De Morgan’s laws –~(a+b) = ~a  ~b –~(a  b) = ~a+~b More… –a+(a  b) = a –a  (a+b) = a –~~a=a You’ll see this again in CS441 and CS1502

20. 20 Examples To get used to Boolean equations To see the relationships among Truth Tables, Boolean Equations, and hardware implementations in gates To see that a “sum of products” formula can always be derived from a truth table To see that equations can often be simplified

21. 21 Example equation E = (A’ B C) + (A B’ C) + (A B C’) What is the value of the equation if A = 1, B = 0 and C = 0? E = (1’ 0 0) + (1 0’ 0) + (1 0 0’) E = (0 0 0) + (1 1 0) + (1 0 1) = 0 What is the value of the equation if A = 0, B = 1, and C = 1? E = (0’ 1 1) + (0 1’ 1) + (0 1 1’) E = (1 1 1) + (0 0 1) + (0 1 0) = 1

22. 22 Truth Table for E ABCDEF 000000 001100 010100 011110 100100 101110 110110 111101 You can read our equation for E right from the truth table: E = (A’ B C) + (A B’ C) + (A B C’) These are the three cases when E is 1. Now, give a Boolean equation for F: F = A B C

23. 23 Give a Boolean Equation for D ABCDEF 000000 001100 010100 011110 100100 101110 110110 111101 D = (A’ B’ C) + (A’ B C’) + (A’ B C) + (A B’ C’) + (A B’ C) + (A B C’) + (A B C) There are many logically equivalent equations (in general) D = (A’ B’ C’)’ [D is true in all cases except A=0 B=0 C=0.] Apply DeMorgan’s law: D = A’’ + B’’ + C’’ = A + B + C

24. 24 Example: boolean equation of a circuit First add the boolean equations at the output for each AND gate A B Y C A B B C

25. 25 Example: Next add the Boolean equations at the output for the OR gate The Boolean equation for the complete logic circuit is: Y = ( A B) + (B C) B C A B Y C A B (A B) + (B C)

26. 26 Example: Truth Table Y = ( A B) + (B C) ABCY 0000 0010 0100 0111 1000 1010 1101 1111 Reading an equation from the Table: Y = (A’ B C) + (A B C’) + (A B C) The equations are logically equivalent: one way to see this is to consider each row in the truth table. If the two equations have the same outputs for each input, then they are logically equivalent.

27. 27 Example: MUX A B S C (A S’) (B S) (A S’) + (B S) ABSC 0000 0010 0100 0111 1001 1010 1101 1111 Equation read from the Table: C = (A’ B S) + (A B’ S’) + (A B S’) + (A B S) Again, the two formulas are equivalent [next slide] If the equation below were implemented directly: four (3-input) AND gates and one (4-input) OR gate would be needed

28. 28 Example: MUX C = (A S’) + (B S) ABSC 0000 0010 0100 0111 1001 1010 1101 1111 C = (A’ B S) + (A B’ S’) + (A B S’) + (A B S) You can see they are equivalent by comparing values for each row BS AS’ If B ==0: (AS’) + 0 If B == 1: 0 + (AS’) So, this is the same as AS’ Methods perform such simplifications automatically

29. 29 Expressive Power Any Boolean algebra function can be constructed using AND gates, OR gates, and Inverters –[For your interest: NAND and NOR are both universal: any logic function can be built with just that one gate type] There are “canonical forms” for Boolean functions: all equations can be expressed in these forms This made it possible to create translation programs that, given a logic equation or truth table as input, can automatically design a circuit that implements it

30. 30 Outline Example to begin: let’s implement a MUX! Gates, Truth Tables, and Logic Equations Combinatorial Logic Constructing an ALU Memory Elements: Flip-flops, Latches, and Registers

31. 31 Since we were talking about MUXs… How are larger MUXs implemented –Wider inputs than 1 bit –More choices

32. 32 A 32-bit wide 2-to-1 Multiplexor Choosing between 2 32-bit wide buses Bus: collection of data lines treated as a single value. E.g., MUX controlled by MemtoReg. 1-bit input to to all 32 MUXs Each MUX is the same; just like the one we saw earlier

33. 33 Use a Decoder to build a MUX with more choices Decoder n bit input value and 2^n outputs I1I2O3O2O1O0 000001 010010 100100 111000 This is a 2-to-4 decoder Appendix C shows the truth table for a 3-to-8 decoder

34. 34 Decoder: implementation with gates Decoder n bit input value and 2^n outputs A = X Y B = X Y C = X Y D = X Y X Y A B C D 000001 010010 100100 111000 D C B AC X Y

35. 35 N input MUX using a decoder Example in lecture

36. 36 Implementing Combinatorial Logic PLA (Programming Logic Array) –A direct implementation of sum of products form pla.html (thanks to: www.cs.umd.edu/class/spring2003/cmsc311/Notes/C omb/pla.html)pla.html ROM (Read Only Memory) –Interpret the truth table as fixed values stored in memory Using logic gate chips (74LS…)

37. 37 74LS Series Chips contain several logic gates SN 74LS08 Quad 2-input AND gate SN 74LS32 Quad 2-input OR gate SN 74LS04 Hex inverter gate

38. 38 ALU Symbol Note that it’s combinational logic

39. 39 Building a 1-bit ALU ALU = Arithmetic Logic Unit

40. 40 Building a 1-bit Adder S = A’B’C in +A’BC in ’+AB’C in ’+ABC in Cout = AB+BC in +AC in (after simplification) E.g., build a pla InputOutput ABC in SC out 00000 00110 01010 01101 10010 10101 11001 11111

41. 41 Building a 32-bit ALU

42. 42 Implementing “SUB”

43. 43 Implementing “NAND”/”NOR”

44. 44 Implementing “SLT”

45. 45 Implementing “SLT”, cont’d

46. 46 0 0 0 Bit 0 Bit 1 Bit 2 Bit 3 4-bit datapath “Operation” same for all “Binvert” same for all “Ainvert” same for all

47. 47 Supporting “BEQ”/”BNE” Need a “zero-detector”

48. 48 ALU Symbol Note that it’s a combinational logic

49. 49 Sequential Logic inputsoutputs …… clock current state next state

50. 50 RS Latch Note that there are feedbacks!

51. 51 RS Latch, cont’d When R=0, S=1 0 10 1 0 1

52. 52 RS Latch, cont’d When R=1, S=0 1 01 0 1 0

53. 53 RS Latch, cont’d When R=0, S=0, and Q was 0 0 01 0 1 0

54. 54 RS Latch, cont’d When R=0, S=0, and Q was 1 0 00 1 0 1

55. 55 RS Latch, cont’d What happens if R=S=1? 1 1

56. 56 D Latch Note that we have an R-S latch as a back-end

57. 57 D Latch, cont’d Note that S, R inputs always get D and inverted input of D when C=1 When C=0, S=R=0, remembering the previous value S R

58. 58 D Latch, cont’d S R CDQ(t) 00Q(t-1) 01 100 111

59. 59 D Latch, cont’d D C Q Q’ D Latch

60. 60 D Flip-Flop (D-FF) Two D latches are cascaded, with opposite clock

61. 61 D Flip-Flop, cont’d D C Q Q’ D-FF

62. 62 Register File Implementation

63. 63 Reg. File Impl., cont’d we’ll return to this in appendix B 1 0x11223344 1 0 0 0 1 1 1 0 0 0