1. Netherlands Institute for Radio Astronomy 1 CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 RadioNET3 WP8 RadioHDL: FPGA Firmware Development for UniBoard 2 CSP SKA-low correlator meeting, Dwingeloo, 26 Nov 2014 Eric Kooistra

2. CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 2 Typical Signal Processing Flow

3. CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 UniBoard 1 3

4. 4 Multi-board solutions CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014

5. 5

6. UniBoard 2

8. UniBoard Comparison UniBoard1 (Stratix IV) UniBoard 2 (Arria10) UniBoard 2 (Stratix10) Throughput rate160 Gbps960 Gbps2400 Gbps Processing2 TMAC/s4.8 TMAC/s20 TMAC/s Nof PCB layers1418 MemoryDDR3DDR4 Technology40nm20nm14nm SerDes3.125 Gbps10 Gbps25 Gbps Operational201220152016

9. CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 9 UniBoard Firmware Platform  Modular design approach based on: - 3 module types : IO, DSP and Control - 2 interface types : Memory Mapped and Streaming data

10. Data reorder and DSP

11. Standard MM and DP streaming interfaces CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 11 Ref.: mnl_avalon_spec.pdf, “Altera Avalon Interface Specifications”

12. Memory-Mapped (MM) interface VHDL records CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 12

13. Data Path (DP) interface VHDL records CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 13

14. Coding style as a tool CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 14  References: - https://svn.astron.nl/UniBoard_FP7/UniBoard/trunk/ Firmware/doc/howto/how_to_write_VHDL.txt - “Clean Code”, R.C. Martin - “The Pragmatic Programmer”, A. Hunt, D. Thomas

15. CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 15 Verification by simulation  Verification is as important as the design itself, they go hand in hand. 1.Test benches with stimuli and verification in VHDL 2.Test benches with stimuli and verification in Python

16. Modelsim add signals command ’The only Logic Analyzer we use’  Use ‘as 10’ to show all signals up to 10 levels of hierarchy in the Modelsim Wave window CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 16

17. RadioHDL  Modular approach like with UniBoard1  More automated tool flow suitable for UniBoard1 and 2  Technology independent with support for StratixIV and Arria10  For more information see: https://svn.astron.nl/UniBoard_FP7/RadioHDL/trunk/tools/hdltool_readme.txt https://svn.astron.nl/UniBoard_FP7/RadioHDL/trunk/libraries/readme_libraries.txt CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 17

18. Modular by using VHDL libraries  Each VHDL library uses the directory name as prefix, eg:  Directory uth/  choose prefix ’uth_’  VHDL library clause name: uth_lib  Components: uth_tx.vhd, uth_rx.vhd, uth.vhd  Testbenches: tb_uth.vh, tb_uth_terminals.vhd  Package: uth_pkg.vhd  Package constants: c_uth_  Package functions: func_uth_  The prefix makes the VHDL library look like a class ! CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 18

19. Automation by using a HDL library config file  Each HDL library directory gets a hdllib.cfg file. A Python script uses this to create the required targets:  hdlib.cfg  modelsim_config.py  Modelsim Project File  hdlib.cfg  quartus_config.py  Quartus Project File  Together with source code the hdllib.cfg defines all that is needed to use the VHDL library in a design.  A design can run on a FPGA and designs are also treated as HDL libraries. CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 19

20. UniBoard 2 test reference design  The unb2_test design is currently being developed within the RadioHDL/ directory.  Purpose of unb2_test is to test all FPGA IO on UniBoard 2 and to serve as a reference design for application designs. CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 20

21. unb2_minimal (only config and control) CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 21

22. unb2_test (all IO) CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 22

23. DSP application for UniBoard 2 CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 23

24. Conclusion CSP SKA-low correlator meeting, Dwingeloo, 24 – 27 November 2014 24  By using the standard DP and MM interfaces the CSP design can focus on the Data Reorder and DSP functionality