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© 2005 Altera Corporation © 2006 Altera Corporation Simulation with Mentor Graphics ModelSim.

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Presentation on theme: "© 2005 Altera Corporation © 2006 Altera Corporation Simulation with Mentor Graphics ModelSim."— Presentation transcript:

1 © 2005 Altera Corporation © 2006 Altera Corporation Simulation with Mentor Graphics ModelSim

2 © 2006 Altera Corporation 2 Objectives Students will be able to: Create working libraries in ModelSim Compile HDL files into working libraries Understand ModelSim projects Run functional simulations using both ModelSim force commands and HDL testbenches Generate all the files in Quartus II required to perform timing simulations

3 © 2006 Altera Corporation 3 PLD Design Flow ModelSim Overview Simulating with ModelSim RTL (Functional) Simulation Gate Level (Timing) Simulation Outline

4 © 2005 Altera Corporation © 2006 Altera Corporation Typical PLD Design Flow

5 © 2006 Altera Corporation 5 Synthesis (Quartus II, Leonardo Spectrum, Synplify, etc.) - Translate Design into Target Technology Primitives - Optimization to Meet Required Area & Performance Constraints Design Specification Place & Route - Map Primitives to Specific Locations Inside Target Technology - Specify Routing Resources to Be Used - May Require Design Edits Design Entry/RTL Coding - Behavioral or Structural Description of Design RTL Simulation (Quartus II or ModelSim®) - Functional Simulation - Verify Logic Model (No Timing Delays) - May Require Design Edits Typical FPGA Design Flow

6 © 2006 Altera Corporation 6 Timing Analysis - Verify Performance Specifications Were Met - May Require Design Edits Gate Level Simulation (Quartus II or ModelSim) - Timing Simulation - Verify Design Will Work in Target Technology - May Require Design Edits PC Board Simulation & Test - Simulate Board Design - Program & Test Device on Board Typical FPGA Design Flow

7 © 2005 Altera Corporation © 2006 Altera Corporation ModelSim Overview

8 © 2006 Altera Corporation Developed by Mentor Graphics One of Industrys Most Popular Simulators Simulates both Verilog & VHDL OEM Version allows for Verilog simulation OR VHDL simulation ModelSim Simulation Tool

9 © 2006 Altera Corporation 9 Complete Standards Support 87 VHDL 93 VHDL IEEE Verilog SDF VITAL 2.2b, VITAL 95, VITAL 2000 Easy-to-use Interface Common across platforms Available for PC, UNIX and Linux environments NativeLink Quartus II can automatically invoke ModelSim after place and route is finished ModelSim OEM Features

10 © 2006 Altera Corporation 10 On-Line Help -> ModelSim Altera Documentation Stored in \docs\ Can also be accessed from Main window Help menu -> PDF Documentation ModelSim Altera Users Manual (oem_man.pdf) Library / Project Management User Interface / Menus ModelSimAltera Command Reference (oem_cmds.pdf) All Model Sim commands and valid arguments ModelSim Altera Tutorial (oem_tutor.pdf) Questions about ModelSim?

11 © 2005 Altera Corporation © 2006 Altera Corporation Simulating with ModelSim

12 © 2006 Altera Corporation Basic Simulation Steps User Interface Functional Simulation Quartus II Output Simulation Files Timing Simulation Agenda

13 © 2006 Altera Corporation 13 ModelSim Execution Methods Graphical User Interface (GUI) Can accept menu input and command line input Main discussion of class Interactive Command Line (Cmd) Only interface is a command line console, no User Interface TCL Scripts and ModelSim Macros TCL – Industry standard scripting language Macros (DO files) – easily created from main window transcripts (GUI commands write equivalent Cmd functions to main window)

14 © 2006 Altera Corporation 14 Basic Simulation Steps Step 1 Create library(s) Step 2 Map library to physical directory Step 3 Compile source code - All HDL Code must be compiled - Different for Verilog and VHDL Step 4 Start simulator and load top-level design unit Step 5 Advance simulator

15 © 2006 Altera Corporation 15 Step 1 Creating ModelSim library(s) GUI) From within Main Window: File -> New -> Library… Cmd) From within Main, transcript window: ModelSim> vlib Example: vlib my_work

16 © 2006 Altera Corporation 16 What are ModelSim Libraries? Directories that contain compiled design units Both VHDL and Verilog are compiled into libraries Two Types Working (default work) Contains the current design unit being compiled Must create a working library before compiling Only one allowed per compilation Resource Contains designs units that can be referenced by the current compilation Multiple allowed during compilation VHDL libraries can be referenced by LIBRARY and USE clauses

17 © 2006 Altera Corporation 17 What are ModelSim Design Units? Primary Must have a unique name in a given library VHDL Entities Package Declarations Configurations Verilog Modules User Defined Primitives Secondary Units in the same library may use a common name VHDL Architectures Package bodies No Verilog secondary units

18 © 2006 Altera Corporation 18 Creating New Libraries (GUI) Select a new library and a logical mapping to it and type library name This command creates a library subdirectory in the local directory and then sets the mapping for it Executing this GUI command produces this at the command prompt transcript: ModelSim > vlib my_lib ModelSim > vmap my_lib my_lib

19 © 2006 Altera Corporation 19 Syntax: vlib Creates libraries Default is work Library contains _info file verilog_module namevhdl_unit name _primary.dat _primary.vhd verilog.psm _primary.dat.dat.asm Where _info - file created so ModelSim recognizes directory as a library _primary.dat - encoded form of Verilog module or VHDL entity _primary.vhd - VHDL entity representation of Verilog ports.dat - encoded form of VHDL architecture verilog.asm and.asm - executable code files Creating New Libraries (GUI)

20 © 2006 Altera Corporation 20 Step 2 Map Logical Library Name(s) GUI) From within Main Window: File -> New -> Library… Cmd) From within Main transcript window: ModelSim> vmap Example: vmap my_work c:\my_design\my_lib Use to map to a library of pre-compiled design units Select a map to an existing library and type library name Browse to library directory

21 © 2006 Altera Corporation 21 Mapping Logical Library Names Must map a Logical Library Name to Library Path (ie. location on hard drive) Files in library path must already have been compiled Relative, absolute, and soft path names supported Needed for libraries not located in the working directory Use vmap command

22 © 2006 Altera Corporation 22 Other Library Commands vdir - Displays the contents of a specified library vdel - Deletes an entire library or a design unit from a specified library GUI) From Main Window Library tab, click + to expand Cmd) vdir -lib library_name> GUI) From Main Window Library tab, right click library or design unit and select Delete Cmd) vdel -lib

23 © 2006 Altera Corporation 23 Step 3 Compile Source Code (VHDL) GUI) Compile -> Compile… Cmd) vcom -work.vhd.vhd Files are compiled in the order they appear Compilation order/dependencies (next slide) 87 VHDL is default GUI) Use Default Options button to set 93 Cmd) Use -93 option (must be first argument) Default compiles into library work Example: vcom -93 my_design.vhd Note: Design units must be re-analyzed when the design units they reference are changed in the library.

24 © 2006 Altera Corporation 24 Step 3 Compile Source Code (Verilog) GUI) Compile -> Compile… Cmd) vlog -work.v.v Files are compiled in the order they appear Order of files or compilation does not matter Supports Incremental Compilation Default compiles into library work Example: vlog my_design.v Note: Design units must be re-analyzed when the design units they reference are changed in the library.

25 © 2006 Altera Corporation 25 Compile (Using GUI) 2). Highlight one or multiple files and click Compile 1). Choose Compile -> Compile…

26 © 2006 Altera Corporation 26 Step 4 Start the Simulator GUI) Simulate -> Simulate… Cmd) vsim VHDL vsim top_entity top_architecture Simulates Entity/Architecture pair Can also choose a Configuration Verilog vsim top_level1 top_level2 Simulates multiple top level Modules

27 © 2006 Altera Corporation 27 Start Simulator (GUI) 3). Choose simulator resolution 2). Select and expand library 4). Select top-level module or entity/architecture, click OK. 1). Choose Simulate -> Simulate…

28 © 2006 Altera Corporation 28 6). Then click OK. 5). For timing simulation, select SDF tab and then Add SDO file Start Simulator (GUI) – continued Type hierarchical level that timing values apply to (if not top level)

29 © 2006 Altera Corporation 29 vsim Command Arguments Arguments -t Specifies simulation time resolution Units can be {fs, ps, ns, ms, sec, min, hr} If Verilog `timescale directives are used, the minimum time precision from all design files will be used Optional (default is ps) -sdfmin | -sdftyp | -sdfmax = Annotates SDF file Optional Using instance names is also optional; If unused, SDF applies to top level

30 © 2006 Altera Corporation 30 vsim Command Arguments Arguments -L (Verilog) Specifies that a particular library should be searched for design units during simulation If multiple libraries are used, each requires the -L option Optional (default is work) -L. Specifies a particular library and design unit to simulate Library name is optional (default is work)

31 © 2006 Altera Corporation 31 Step 5 Advance Simulator GUI) Simulate -> Run Cmd) run Advances the simulator in the amount of timesteps specified

32 © 2006 Altera Corporation 32 Advance Simulator (GUI) Restart - Reloads any design elements that have been edited and resets the simulation time to zero Cmd) restart Choose the number of timesteps to advance the simulator

33 © 2006 Altera Corporation 33 run Command Arguments Optional Arguments - Specifies the number of timesteps to run Units can be {fs, ps, ns, ms, sec} -step Steps to the next HDL statement -over Steps to the next HDL statement Treats VHDL procedures, functions, and Verilog tasks as single executable

34 © 2006 Altera Corporation 34 run Command Arguments Optional Arguments -continue Continues the last simulation after a -step, step -over or breakpoint -all Runs simulator until no more events are scheduled Maximum simulation time is 2 64 timesteps

35 © 2006 Altera Corporation 35 Breaking Simulation run Use Break Key to stop (pause) simulator while advancing Break Key

36 © 2006 Altera Corporation 36 Simulator Stimulus Force Commands Simple module simulation Directly from command console.DO file (macro file) Testbench Verilog or VHDL Very complex simulation interactive simulation

37 © 2006 Altera Corporation 37 force Command Allows user to apply stimulus to VHDL signals and Verilog nets General Syntax: force, Arguments item_name The name of the HDL item to be forced Required / indicates hierarchical levels Must be a scalar or one-dimensional array of characters Can be an indexed array, array slice, or record sub- element as long as its of the above type Can use wildcards as long as only one match is obtained

38 © 2006 Altera Corporation 38 force Command (cont.) More Arguments value Value to which the item is forced Must fit items data type Required time Specifies the time unit for the value Relative to current simulation time character to specify absolute time Time units can be specified Default is simulation resolution units Optional

39 © 2006 Altera Corporation 39 force Command (cont.) More Arguments -r[epeat] Repeats the force command for the specified period Optional -cancel Cancels the force command after the specified period Optional

40 © 2006 Altera Corporation 40 DO Files Macro file for automating simulation steps Library setup Compiling Simulating Forcing simulator stimulus Can be invoked in all ModelSim modes GUI) Tools -> Execute Macro… Cmd) do.do Can call other DO files cd c:\mydir vlib work vcom counter.vhd vsim counter view * add wave /* add list /* do run.do

41 © 2006 Altera Corporation 41 Debugging Designs When to debug? Unsuccessful compilation Incorrect or unexpected simulation results Example ModelSim Debugging Capabilities Signal Monitoring Breakpoints

42 © 2006 Altera Corporation 42 Monitoring More Signals Add additional signals or variables for tracking Select region in Structure window or the sim tab of the main window workspace. drag and drop from Source, Signals or Variables windows to: Wave window List window

43 © 2006 Altera Corporation 43 Breakpoints Two types of breakpoints are supported Breakpoints on line(s) in source code window Toggles - click again to delete existing breakpoint No limit to the number of break points Use command bp bp Conditional break points when when {b=1 and c/=0} Used with VHDL signals and Verilog nets and registers Use command bp also bp {if{$now/=100}then{cont}}

44 © 2006 Altera Corporation 44 modelsim.ini file An ASCII file used by ModelSim, controlled by the user A default file is provided in the ModelSim installation directory modelsim.ini is used by the compiler and the simulator Stores initialization information Location of libraries location of startup file Other default settings for ModelSim ModelSim searches for the modelsim.ini in the following order: 1. Environment variable called MODELSIM which points directly to the modelsim.ini file to be used 2. A file called modelsim.ini located in the current working directory 3. The default modelsim.ini file in the ModelSim software installation tree

45 © 2006 Altera Corporation 45 startup.do file A DO script automatically executed by vsim upon startup An example startup.do file might look like this: view source view structure view wave do wave.do To invoke a startup file, uncomment (remove the ; from) the following line in the modelsim.ini file and provide path to the do file: ;Startup = do / /startup.do

46 © 2006 Altera Corporation 46 ModelSim Projects Projects are a collection of entities for HDL designs under specification or test Projects are stored as.MPF file in the project directory and contain: Root directory and subdirectories work library and other project libraries or references to libraries HDL source files or references to source files Compiler and simulator settings Allows you to save current work session Used mostly with GUI Project Operations File -> New / Open / Close / Delete

47 © 2006 Altera Corporation 47 Benefits of Using Projects in ModelSim Simplifies interaction with ModelSim Compile order of source files is maintained in project Compiler settings and switches are stored in project Allows for easy sharing of libraries without copying files to a local directory Creating a project creates your work library automatically The project.MPF file contains all of the settings in the main modelsim.ini file located in the ModelSim install directory

48 © 2006 Altera Corporation 48 Applying ModelSim to the PLD Design Flow

49 © 2006 Altera Corporation 49 System Production Design Specification Typical PLD Flow Design Entry RTL Simulation Design Synthesis Gate Level Simulation Place & Route Timing Analysis In-System Verification Design Modification ModelSim

50 © 2006 Altera Corporation 50 RTL (Functional) Simulation Pre-Place & Route Simulation Test Logical Model Perform the Basic Simulation Steps on Design Files Exception: Using LPMs or MegaWizard Generated Functions Must Map to Simulation Models Stored in \altera Directory

51 © 2006 Altera Corporation 51 LPM Simulation Models (Verilog) Pre-Compiled Simulation Models for Standard LPM Functions ModelSim OEM Only Examples LPM_ADD_SUB LPM_COUNTER LPM_MULT Library 220model_ver Pre-Mapped to Directory \altera\verilog\220model Specify Library 220model_ver when Starting Simulator LPM_RAM_DP LPM_RAM_DQ LPM_AND / LPM_OR

52 © 2006 Altera Corporation 52 Verilog LPM Simulation Cmd) vsim –L 220model_ver GUI) When loading the design, click on the Libraries tab. Click Add and browse to the 220model directory: \\altera\verilog \220model

53 © 2006 Altera Corporation 53 LPM Simulation Models (VHDL) Pre-Compiled Simulation Models for Standard LPM Functions ModelSim OEM Only Examples LPM_ADD_SUB LPM_COUNTER LPM_MULT User Must Map Library to \altera\vhdl\220model Directory Type LIBRARY & USE Clauses in Design File (added automatically by MegaWizard for examples above) LIBRARY ; USE.lpm_components.all: LPM_RAM_DQ LPM_RAM_DP LPM_AND / LPM_OR

54 © 2006 Altera Corporation 54 Altera Megafunction Models (Verilog) Pre-compiled Simulation Models for Altera-Specific Megafunctions ModelSim OEM Only Examples ALTCDR_RX or ALTCDR_TX (Clock Data Recovery) ALTQPRAM (Quad-Port RAM) ALTCAM (Content Addressable Memory) ALTCLOCKLOCK (PLL) Library altera_mf_ver Pre-mapped to Directory \altera\verilog\altera_mf Specify Library altera_mf_ver When Starting Simulator

55 © 2006 Altera Corporation 55 Altera Megafunction Models (VHDL) Pre-compiled Simulation Models for Altera-Specific Megafunctions ModelSim OEM Only Examples ALTCDR_RX or ALTCDR_TX (Clock Data Recovery) ALTQPRAM (Quad-Port RAM) ALTCAM (Content Addressable Memory) ALTCLOCKLOCK (PLL) Library altera_mf Pre-Mapped to \altera\vhdl\altera_mf Type LIBRARY & USE Clauses in Design File (added automatically by MegaWizard for examples above) LIBRARY altera_mf; USE altera_mf.altera_mf_components.all:

56 © 2006 Altera Corporation 56 Testbench In the early days of HDLs, stimulus and verification was made through proprietary simulator methodologies Vector waveform files (Quartus II) Force Files (Mentor Graphics) Testbench not portable between tools Using a testbench written in HDL simplified design flow and increased portability

57 © 2006 Altera Corporation 57 Three Classes of Testbenches I.Test bench applies stimulus to target code and outputs are manually reviewed II.Test bench applies stimulus to target code and verifies outputs functionally Requires static timing analysis III.Test bench applies stimulus to target code and verifies outputs with timing Does not require full static timing analysis Code and test bench data more complex

58 © 2006 Altera Corporation 58 Class I Simplest to write (no verification code) Requires manual verification (usually visual) Original designer who fully understands code can more easily understand waveforms and timing Different engineer may miss errors or take much longer to understand target code to verify manually Best used for simpler target code & code not intended for re-use

59 © 2006 Altera Corporation 59 Class II Harder to write and debug initially Writing expected results vectors requires deep understanding of target code and can typically help make code better by forcing engineer to do more work up front Fallback is that errors in the expected results vectors can be hard to catch Benefit is that you can set it and forget it (besides static timing analysis / timing simulation)

60 © 2006 Altera Corporation 60 Class III Much harder to write and debug initially Writing expected results vectors requires deep understanding of both target code and timing information – setup and hold times for clock edges checked Can require substantial changes to both testbench and vectors every time a design or process change occurs Most in-depth of test benches but can be overkill for most situations

61 © 2006 Altera Corporation 61 ENTITY gatetest IS END gatetest; ARCHITECTURE stimulus OF gatetest IS COMPONENT simplegate PORT (A,B: IN std_logic; Y: OUT std_logic); END COMPONENT; SIGNAL A,B,Y: std_logic; BEGIN NAND1: simplegate PORT MAP(A => A,B => B,Y => Y); PROCESS CONSTANT period : TIME := 40 ns; BEGIN A <= '1'; B <= '1'; WAIT FOR period; A <= '1'; B <= '0'; WAIT FOR period; A <= '0'; B <= '1'; WAIT FOR period; A <= '0'; B <= '0'; WAIT FOR period; WAIT; END PROCESS; END stimulus; Sample VHDL Class I Testbench Declare Lower-Level Design Entity Top-Level Entity Has No Ports Signals to Assign Values & Observe Instantiate Lower-Level Entity Process to Apply Stimulus Final WAIT Keeps Process from Repeating Indefinitely

62 © 2006 Altera Corporation 62 module gatetest(); parameter period = 40; reg A,B; wire Y; NAND1 u1(.A(A),.B(B),.Y(Y)); initial begin A = 1; B = 1; #period; A = 1; B = 0; #period; A = 0; B = 1; #period; A = 0; B = 0; #period; end endmodule Sample Verilog Class I Testbench Top-Level Entity Has No Ports Signals to Assign Values & Observe Instantiate Lower-Level Entity Apply Stimulus

63 © 2006 Altera Corporation 63 System Production Design Specification Typical PLD Flow Design Entry RTL Simulation In-System Verification Design Modification ModelSim Timing Analysis Place & Route Design Synthesis Gate Level Simulation

64 © 2006 Altera Corporation 64 Performing Post P&R (Timing) Simulation 1) EDA Tool Settings to ModelSim Verilog or VHDL 2) Compile Design in Quartus II to Produce Output Files 3) Create Testbench / Stimulus - Can Use Stimulus From RTL Simulation 4) Perform Basic Simulation Steps - Compile Quartus II Output File - Map to ATOM Libraries - Include SDO (SDF format) File When Loading Design

65 © 2006 Altera Corporation 65 Before Compilation Assignments Menu -> EDA Tool Settings…

66 © 2006 Altera Corporation 66 NativeLink Automatically starts ModelSim and compiles the Quartus II output file after compilation is finished

67 © 2006 Altera Corporation 67 Specify Path to Simulator Tools Options EDA Tool Options Double-click to specify path to simulation tool executable

68 © 2006 Altera Corporation 68 Enable NativeLink Settings None NativeLink compiles simulation models & design files Compile test bench NativeLink compiles all files (including test bench) and starts simulation Use script to compile test bench NativeLink compiles simulation models & design files User specifies script to compile test bench and start simulator

69 © 2006 Altera Corporation 69 Setting Up Test Benches Create test bench settings for each test bench to be simulated

70 © 2006 Altera Corporation 70 Running NativeLink Simulation Tools EDA Simulation Tool Select RTL or Gate- level simulation

71 © 2006 Altera Corporation 71 Post Place & Route Simulation Files Compile Design in Quartus II to Produce Output Files Output Simulation Files from Quartus II. VO - Verilog Output File.VHO - VHDL Output File.SDO - Standard Delay Format (SDF) Output File Annotates the delay for the elements in the output files Design files -.EDF -.VQM -.V -.VHD.VO.VHO.SDO

72 © 2006 Altera Corporation 72 Pre-Compiled Design Units are Provided for RTL and Post Place and Route Simulation For OEM ModelSim only For MSE and MPE, uncompiled source code is provided (with the exception of Stratix GX libraries which are always pre-compiled) Mapping Libraries If you create a ModelSim project, all device families libraries are pre-mapped for you. Otherwise, you must map each device family individually eg. Stratix,Cyclone, etc. Device Libraries Would Be Manually Mapped Map stratixii_ver to \altera\verilog\stratixii Map cyclone_ver to \altera\verilog\cyclone ATOM Simulation Files (Verilog)

73 © 2006 Altera Corporation 73 ATOM Simulation Files (Verilog) Specify Appropriate Library When Starting Simulator -L stratixii_ver -L stratix_ver -L cyclone_ver -L stratixgx_ver -L apex20ke_ver Command Line GUI

74 © 2006 Altera Corporation 74 ATOM Simulation Files (VHDL) Pre-Compiled Design Units Are Provided for RTL and Post Place & Route Simulation For OEM ModelSim only And for MSE and MPE, uncompiled source code is provided (with the exception of Stratix GX libraries which are always pre-compiled) LIBRARY & USE Clauses Already Written in.VHO File LIBRARY alt_vtl; USE ALT_VTL..all Mapping Libraries Unless you use ModelSim Projects, you must map to alt_vtl library to: /altera/vhdl/stratixii /altera/vhdl/cyclone /altera/vhdl/stratixgx /altera/vhdl/apex20ke

75 © 2006 Altera Corporation 75 SDF Annotation Click on SDF Tab to assign timing file Click Add button Specify the SDO file and the Apply Region

76 © 2006 Altera Corporation 76 Exercise Please go to Exercise

77 © 2006 Altera Corporation 77 Exercise Summary Functional Simulation w/ModelSim Use Pre-Compiled ModelSim Libraries Timing Simulation w/ModelSim Quartus II EDA Tool Settings Mapping to correct simulation models

78 © 2006 Altera Corporation 78 ModelSim Basic Simulation Review cd Into Working Directory Create Working Library to Compile Design Units Into (Optional) Map to Libraries of Pre-Compiled Design Units Compile All Design Units Into Library Note: must compile from bottom-up when using VHDL Add SDO File From Quartus II (If Performing Timing-Simulation) Link in Behavioural or Device-Specific Libraries As Required Load Top-Level Design (or testbench) Into Simulator and Set Simulator Resolution Open Wave Window and Add Signals You Are Interested In Apply Force Commands (If A Testbench Not Used) Advance Simulator to Generate Vectors in Wave Window Debug Your Design

79 © 2006 Altera Corporation 79 PLD Design Flow ModelSim Overview Simulating with ModelSim RTL (Functional) Simulation Gate Level (Timing) Simulation Class Summary


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