1. Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link) 06.02.2013 wacek ostrowicz 14 slides The Prototype of the SVD FTB Recent Status for PXD+SVD combined DAQ session on Wednesday at 3rd Belle II PXD/SVD Workshop and 12th International Workshop on DEPFET Detectors and Applications in Wetzlar, Germany 4-6 February 2013

2. I. SVD Electronics - general view II. Status of Hardware III. Status of Firmware IV. Schedule V. Summary Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link) 06.02.2013 wacek ostrowicz1/14

3. SVD Electronics - g eneral view PIXEL DAQ F E E l e c t r o n i c s COPPER#4 8 opt FRB COPPER#1 opt FRB … SVD electronics Giessen Box opt #1#48 SVD tracker … FTB# 48 FADC#48 RJ45 opt RJ45 opt FTB#1 FADC#1 RJ45 opt RJ45 opt FADC- CONTROLLER (FADCctlr) RJ45 FTSW RJ45 #1 #49 #48 RJ45 … TTD JTAG 06.02.2013 wacek ostrowicz2/14 Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

4. II. Status of Hardware 1. PCB Design version2 2. List of changes 3. TTD and GTP Clock distribution. Clock Domains 06.02.2013 wacek ostrowicz3/14 Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

5. FTB Prototype version2 6 2 1 4 35 7 8 8 06.02.2013 wacek ostrowicz4/14 Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

6. List of changes 1. LVDS outputs for TTD moved to Bank2 2. One Oscillator 127MHz + DS25CP152 chip. 3. TTD Clk connected to GTP RefClk pins. 4. 32MHz Oscillator on board 5. Third OptoLink 6. Different drivers 7. Changed pin-out 8. XC6SLX75T -> XC6SLX100T Logic Cells: 74,637 -> 101,261 Slices: 11,662 -> 15,822 Max Distributed RAM (Kb): 692 -> 976 Block RAM Blocks [Max (Kb)]: 3,096 -> 4,824 Price: $140 -> $176 9. Module equipped with Front Plate -> no backplane between FADC and FTB 06.02.2013 wacek ostrowicz5/14 Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

7. Oscillator 127MHz RJ 45 MUX DS25CP152 Diff Input FPGA 127MHz REFCLK0 REFCLK1 GTP X0Y0 from/to TTD SELECT[1:0] ENABLE TTD core Gclk 127 MHz 32 MHz & FPGA init FTBRDY FADCRDY FADC DCLK DATA TTD core MUX 127MHz from TTD GTP Clk FTBFPGA Main Part of FPGA GTP Trans ceiver ADC&FTB READY Opto Transceiver TTD and GTP Clock distribution. Clock Domains. 06.02.2013 wacek ostrowicz6/14 Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

8. III. Status of Firmware 1. Receive DATA from FADC 2. Input DATA CRC checking 3. Receive EventNumber and Trigger from DAQ and calculate FTB_EventNumber 4. Checking and reporting differences with Event Number coming from DAQ, FADC and FTB 5. Inserting HEADER and TRAILER 6. Output DATA CRC calculation. 7. Preparing DATA and control signals for BELLE2 Universal Core. 06.02.2013 wacek ostrowicz7/14 a) main goals of FTB Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

9. 06.02.2013 wacek ostrowicz8/14 main goals of FTB cont… Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

10. III. Status of Firmware 1. Interface between FTB and FADC 2. Interface between FTB core and Belle2Link core 3. Interface between FTB core and PXD core 4. Interface between FTB core and TTD core 06.02.2013 wacek ostrowicz9/14 b) FTB Interfaces FADC TTD core FTSW (TTD) FTB FPGA Main Part of FPGA Opto Transceiver B2L core PXD core RJ45 FTSW (JTAG) PXD B2Link 1 2 3 4 Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

11. 06.02.2010 wacek ostrowicz10/14 DATA format -> FF[31:0] -> FWENB -> FWCLK <- FFUL <- NWFF COPPER FINESSE -> BSYB <- TAG[7:0] <- TRG <- CLK <- IRSTB <> LD[7:0] <- LA[6:0] <- LRW <- CSB -> FRSTB Universal part IDENTICAL for ALL subdetectors Part dependent on subdetector Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

12. OpTr DATA( 31:0) Logic OpTr Unified core for HSD Link Core for PXD Link MAIN FIFO for HSD Link >120kB FIFO for PXD Link HSD Link To PXD Output FIFO Event Rdy write FIFO end of Event FIFO empty FIFO full HSD Link side requires to collect the whole Event before sending out 06.02.2013 wacek ostrowicz11/14 III. Status of Firmware b) interface to OptoLinks for DATA - proposal SVD Logic FIFO full FIFO empty BoE EoE write FIFO DCLK Read FIFO DCLK Read FIFO FIFO full GTP CLK Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

13. III. Status of Firmware 1. Interface between FTB core and Belle2Link core 2. Interface between FTB core and TTD core 3. Remote FPGA configuration 4. Interface between FTB core and on board serial PROM No significant progress since last B2GM meeting 06.02.2013 wacek ostrowicz12/14 c) what has to be done Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

14. IV. Schedule PCB design is ready Production of the PCB Ordering the parts Mounting modules Basic tests of the modules Distribution 1 module to KEK 1 module to PXD 2 modules remain in Krakow (will be used for DESY test) 1 spare module to ??? Production of 5 modules of the FTB module ver2. 06.02.2013 wacek ostrowicz13/14 January February March April Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)

15. IV. Summary The most important and urgent goals: 1. Start the PCB production. 2. Agree on the Interface between Belle2Link core and FTB core 3. Start the Modules production 3. Agree on the Interface between TTD core and FTB core 4. Finish full FTB firmware. Thank you 06.02.2013 wacek ostrowicz14/14 Prototype of the SVD Finesse Transmitter Board (FTB) (Sender Part for HSD Link)