1. UNIT 8 COMBINATIONAL CIRCUIT DESIGN AND SIMULATION USING GATES
This chapter in the book includes:
Objectives
Study Guide
8.1 Review of Combinational Circuit Design
8.2 Design Circuits with Limited Gate Fan-In
8.3 Gate Delays and Timing Diagrams
8.4 Hazards in Combinational Logic
8.5 Simulation and Testing of Logic Circuits
Problems
Design Problems
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2. Design of Circuits with Limited Gate Fan-In
In practical logic design problems, the maximum number of inputs on each gate (or the fan-in) is limited.
If a two-level realization of a circuit requires more gate inputs than allowed, factoring the logic expression to obtain a multi-level realization is necessary.
Section 8.2 (p. 220)

3. Example 1 00 01 11 10 First we find a minimum sum-of-products of f ′.
Realize f(a, b, c, d) = Ʃ m(0, 3, 4, 5, 8, 9, 10, 14, 15) using three-input NOR gates. 00 01 11 10
First we find a minimum sum-of-products of f ′. 00 01 11 10
Section 8.2 (p. 220)

4. Then the expression for f ′ is factored to reduce the maximum number of gate inputs to three and, then it is complemented.
f ′ = b′d(a′c′ + ac) + a′c(b + d′) + abc′
f = [b + d′ + (a + c)(a′ + c′)][a + c′ + b′d] [a′ + b′ + c]
Figure 8-1

5. Figure 8-2 Example 2 f1 = b′c′ + ab′ + a′b f2 = b′c′ + bc + a′b
Realize the functions given in Figure 8-2, using only two-input NAND gates and inverters. If we minimize each function separately, the result is
f1 = b′c′ + ab′ + a′b
f2 = b′c′ + bc + a′b
f3 = a′b′c + ab + bc′
Figure 8-2

6. a′b′c = a′(b′c) = a′(b + c′)′
Each function requires a three-input OR gate, so we will factor to reduce the number of gate inputs:
f1 = b′(a + c′) + a′b
f2 = b(a′ + c) + b′c′ or f2 = (b′ + c)(b + c′) + a′b
f3 = a′b′c + b(a + c′)
The second expression for f2 has a term common to f1, so we will choose the second expression. We can eliminate the remaining three-input gate from f3 by noting that
a′b′c = a′(b′c) = a′(b + c′)′

7. Figure 8-3: Realization of Figure 8-2

8. Gate Delays and Timing Diagrams
When the input to a logic gate is changed, the output will not change instantaneously. The transistors or other switching elements within the gate take a finite time to react to a change in input, so that the change in the gate output is delayed with respect to the input change.
Section 8.3 (p. 222)

9. Figure 8-4: Propagation Delay in an Inverter

10. Figure 8-5: Timing Diagram for AND-NOR Circuit

11. Figure 8-6: Timing Diagram for Circuit with Delay

12. Introduction (1/2) Two classes of logic circuits:
combinational
sequential
Combinational Circuit:
Combinational
Logic
: :
inputs
outputs
Each output depends entirely on the immediate (present) inputs.

13. Introduction (2/2) Sequential Circuit: (not covered) Combinational
Logic
: :
inputs
outputs
Memory
Output depends on both present and past inputs.
Memory (via feedback loop) contains past information.

14. Analysis Procedure
Given a combinational circuit, can you analyze its function?
A+B
A'+B'
= (A+B).(A'+B')
= (A'+B')' = A.B AB F1 F2
Steps:
1. Label the inputs and outputs.
2. Obtain the functions of intermediate points and the outputs.
3. Draw the truth table.
4. Deduce the functionality of the circuit  half adder.

15. Design Methods (1/2) Different combinational circuit design methods:
Gate-level method (with logic gates)
Block-level design method
Design methods make use of logic gates and useful functional blocks.
These are available as Integrated Circuit (IC) chips.

16. Design Methods (2/2) Type of IC chips (based on packing density) :
Small-scale integration (SSI): up to 12 gates
Medium-scale integration (MSI): gates
Large-scale integration (LSI): gates
Very large-scale integration (VLSI): 10,000-99,999 gates
Ultra large-scale integration (ULSI): > 100,000 gates
Main objectives of circuit design:
(i) reduce cost
reduce number of gates (for SSI circuits)
reduce IC packages (for complex circuits)
(ii) increase speed
(iii) design simplicity (reuse blocks where possible)

17. Gate-level (SSI) Design: Half Adder (1/2)
Design procedure:
1) State Problem
Example: Build a Half Adder to add two bits
2) Determine and label the inputs & outputs of circuit.
Example: Two inputs and two outputs labelled, as follows:
Half
Adder X Y S C
(X + Y)
3) Draw truth table.

18. Gate-level (SSI) Design: Half Adder (2/2)
4) Obtain simplified Boolean function.
Example: C = X.Y
S = X'.Y + X.Y' = XY
5) Draw logic diagram. X Y S C
Half Adder

19. Gate-level (SSI) Design: Full Adder (1/5)
Half-adder adds up only two bits.
To add two binary numbers, we need to add 3 bits (including the carry).
Example:
Need Full Adder (so called as it can be made from two half-adders).
Full
Adder X Y Z S C
(X + Y + Z)

20. Gate-level (SSI) Design: Full Adder (2/5)
Truth table:
Note:
Z - carry in (to the current position)
C - carry out (to the next position) 1 X YZ C S
Using K-map, simplified SOP form:
C = X.Y + X.Z + Y.Z
S = X'.Y'.Z + X'.Y.Z'+X.Y'.Z'+X.Y.Z

21. Gate-level (SSI) Design: Full Adder (3/5)
Alternative formulae using algebraic manipulation:
C = X.Y + X.Z + Y.Z
= X.Y + (X + Y).Z
= X.Y + ((XY) + X.Y).Z
= X.Y + (XY).Z + X.Y.Z
= X.Y + (XY).Z
S = X'.Y'.Z + X'.Y.Z' + X.Y'.Z' + X.Y.Z
= X‘.(Y'.Z + Y.Z') + X.(Y'.Z' + Y.Z)
= X'.(YZ) + X.(YZ)'
= X(YZ) or (XY)Z

22. Gate-level (SSI) Design: Full Adder (4/5)
Circuit for above formulae:
C = X.Y + (XY).Z
S = (XY)Z
(XY) X Y S C Z
(XY)
Full Adder made from two Half-Adders (+ OR gate).

23. Gate-level (SSI) Design: Full Adder (5/5)
Circuit for above formulae:
C = X.Y + (XY).Z
S = (XY)Z
Block diagrams.
Half
Adder X Y
Sum
Carry
(XY) X Y S C Z
(X.Y)
Full Adder made from two Half-Adders (+ OR gate).

24. Code Converters
Code converters – take an input code, translate to its equivalent output code.
Code
converter
Input
code
Output
Example: BCD to Excess-3 Code Converter.
Input: BCD digit
Output: Excess-3 digit

25. BCD-to-Excess-3 Code Converter (1/2)
Truth table:
K-maps: 1 A C 00 01 11 10 D AB CD B X W Y Z

26. BCD-to-Excess-3 Code Converter (2/2)A C 00 01 11 10 D AB CD B X 1 W A C 00 01 11 10 D AB CD B X 1
W = A + B.C + B.D
X = B'.C + B‘.D + B.C'.D'
Y = C.D + C'.D'
Z = D' A C 00 01 11 10 D AB CD B X 1 Y 1 A C 00 01 11 10 D AB CD B X Z

27. Block-Level Design Method
More complex circuits can also be built using block-level method.
In general, block-level design method (as opposed to gate-level design) relies on algorithms or formulae of the circuit, which are obtained by decomposing the main problem to sub-problems recursively (until small enough to be directly solved by blocks of circuits).
Simple examples using 4-bit parallel adder as building blocks:
(1) BCD-to-Excess-3 Code Conversion
(2) 16-Bit Parallel Adder
(3) Adder cum Subtractor

28. 4-bit Parallel Adder (1/4)
Consider a circuit to add two 4-bit numbers together and a carry-in, to produce a 5-bit result:
4-bit
Parallel Adder C5 C1 X2 X1 Y4 Y3 S4 S3 S2 S1 Y2 Y1 X4 X3
Black-box view of 4-bit parallel adder
5-bit result is sufficient because the largest result is:
(1111)2+(1111)2+(1)2 = (11111)2

29. 4-bit Parallel Adder (2/4)
SSI design technique should not be used.
Truth table for 9 inputs very big, i.e. 29=512 entries:
Simplification very complicated.

30. 4-bit Parallel Adder (3/4)
Alternative design possible.
Addition formulae for each pair of bits (with carry in),
Ci+1Si = Xi + Yi + Ci
has the same function as a full adder.
Ci+1 = Xi .Yi + (Xi  Yi ) .Ci
Si = Xi  Yi  Ci

31. 4-bit Parallel Adder (4/4)
Cascading 4 full adders via their carries, we get: C1
Y1 X1 S1 FA C2 C5
Y2 X2 S2 C3
Y3 X3 S3 C4
Y4 X4 S4
Output
Input

32. Parallel Adders
Note that carry propagated by cascading the carry from one full adder to the next.
Called Parallel Adder because inputs are presented simultaneously (in parallel). Also, called Ripple-Carry Adder.

33. BCD-to-Excess-3 Code Converter (1/2)
Excess-3 code can be converted from BCD code using truth table:
Gate-level design can be used since only 4 inputs.
However, alternative design possible.
Use problem-specific formulae:
Excess-3 Code
= BCD Code + (0011)2

34. BCD-to-Excess-3 Code Converter (2/2)
Excess-3 Code = BCD Code + (0011)2
Block-level circuit:
4-bit Parallel Adder X4 X3 X2 X1 Y4 Y3 Y2 Y1 1 S4 S3 S2 S1
BCD
code
Excess-3
unused
Cin
Cout
A BCD-to-Excess-3 Code Converter

35. 16-bit Parallel Adder (1/2)
Larger parallel adders can be built from smaller ones.
Example: a 16-bit parallel adder can be constructed from four 4-bit parallel adders:
4-bit // adder
X4..X1
Y4..Y1 C1
S4..S1
X8..X5
Y8..Y5 C5
S8..S5
X12..X9
Y12..Y9 C9
S12..S9
X16..X13
Y16..Y13
C13
S16..S13
C17 4
A 16-bit parallel adder

36. 16-bit Parallel Adder (2/2)
Shortened notation for multiple lines. 4
S4 .. S1
S4 S3 S2 S1
is a shortened notation for
16-bit parallel adder ripples carry from one 4-bit block to the next.
Such ripple-carry circuits are “slow” because of long delays needed to propagate the carries.

37. 4-bit Parallel Adder cum Subtractor (1/4)
Subtraction can be performed through addition using 2s-complement numbers.
Hence, we can design a circuit which can perform both addition and subtraction, using a parallel adder.
4-bit adder
cum subtractor
S: control signal for add/subtract X2 X1 Y4 Y3
Result: either X+Y or X-Y Y2 Y1 X4 X3

38. 4-bit Parallel Adder cum Subtractor (2/4)
The control signal S=0 means add
S=1 means subtract
Recall that:
X-Y = X + (-Y)
= X + (2’s complement of Y)
= X + (1’s complement of Y) +1
X+Y = X + (Y)

39. 4-bit Parallel Adder cum Subtractor (3/4)
Design requires:
(i) XOR gates:
S = 0 Y
S = 1 Y' Y
such that: output = Y when S=0
= Y' when S=1
(ii) S connected to carry-in.

40. 4-bit Parallel Adder cum Subtractor (4/4)
Adder cum subtractor circuit:
4-bit
parallel adder X2 X1 Y4 Y3 Y2 Y1 X4 X3 S2 S1 S4 S3 C S
Cin
Cout
Analysis:
If S=1, then
X + (1's complement of Y) +1
appears as the result.
If S=0, then X+Y appears as
the result.
A 4-bit adder cum subtractor

41. Arithmetic Circuits: Adders
Revision
Half adder X Y S
Cout
Sum
Carry
Input bits
Output bits x y'
S = xy' + x'y x' y C x' y'
S = (C+x'y')' x y C x y
S = (x+y)(x'+y') x' y' C x y C
S = x  y

42. Arithmetic Circuits: Adders
Revision
Full adder
Sum
Carry
Input bits
Output bits A B S
Cout
Cin 1 x yz
C = xy + xz + yz 1
S = x'y'z + x'yz' + xy'z' + xyz x yz X' y' z S x' y z' x C x y
S = (xy)z
C = xy + (xy)z z
xy xy

43. Arithmetic Circuits: Parallel Adders
Revision
Example: Adding two 4-bit numbers
2 ways:
Serial (one FA)
Parallel (n FAs for n bits) C1
Y1 X1 S1 C2 C5
Y2 X2 S2 C3
Y3 X3 S3 C4
Y4 X4 S4 FA X Y S
Cout
Cin
Input carry
Binary no. B
Binary no. A
Output carry
4-bit sum

44. Arithmetic Circuits: Cascading Adders
Revision
4-bit parallel adder:
cascade 4 full adders
classical method: 9 input variables  29 = 512 rows in truth table!
Cascading method can be extended to larger numbers, example: 16-bit parallel adder.
4-bit // adder
X4..X1
Y4..Y1 C1
S4..S1
X8..X5
Y8..Y5 C5
S8..S5
X12..X9
Y12..Y9 C9
S12..S9
X16..X13
Y16..Y13
C13
S16..S13
C17 4

45. Arithmetic Circuits: Cascading Adders
Application: 6-person voting system.
Use FAs and a 4-bit binary parallel adder.
Each FA can sum up to 3 votes.
Voter 1
3-bit Output A B S
Cout
Cin
Voter 2
Voter 3
Voter 4
Voter 5
Voter 6
Full-adder 1
Full-adder 2 1 2 3 4
Parallel adder

46. Arithmetic Circuits: Adder-Subtractor
Revision
Make use of 2’s complement:
X - Y = X + (-Y)
2’s complement of Y = Inverting bits in Y and plus 1.
4-bit
parallel adder X2 X1 Y4 Y3 Y2 Y1 X4 X3 S2 S1 S4 S3 C S
Cin
Cout Z4 Z3 Z2 Z1
Zi = S.Yi' + S'.Yi
When S=0,
Cin=0, Zi = Yi  S = X + Y
When S=1,
Cin=1, Zi = Yi'  S = X + Y' + 1

47. Arithmetic Circuits: Comparator (1/3)
Magnitude comparator: compares 2 values A and B, to see if A>B, A=B or A<B.
Classical method requires 22n rows in truth table!
We exploit regularity.
How do we compare two 4-bit values A (a3a2a1a0) and B (b3b2b1b0)?
If (a3 > b3) then A > B
If (a3 < b3) then A < B
If (a3 = b3) then if (a2 > b2) ….

48. Equality Comparator XNOR X Y Z 0 0 1 0 1 0 X 1 0 0 Z 1 1 1 Y X Z Y
Z = !(X $ Y)

49. 4-Bit Equality Comparator
FIELD A = [A0..3];
FIELD B = [B0..3];
FIELD C = [C0..3];

50. 4-bit Equality Detector
A_EQ_B
B[3..0]

51. 4-bit Magnitude Comparator
A_LT_B
A[3..0]
Magnitude
Detector
A_EQ_B
B[3..0]
A_GT_B

52. Magnitude Comparator How can we find A_GT_B?
How many rows would a truth table have?
28 = 256!

53. Magnitude Comparator Find A_GT_B Because A3 > B3 i.e. A3 & !B3 = 1
If A = 1001 and
B = 0111
is A > B?
Why?
Therefore, one term in the
logic equation for A_GT_B is
A3 & !B3

54. Magnitude Comparator A_GT_B = A3 & !B3 + ….. Because A3 = B3 and
+ …..
Because A3 = B3 and
A2 > B2
i.e. C3 = 1 and
A2 & !B2 = 1
If A = 1101 and
B = 1011
is A > B?
Why?
Therefore, the next term in the
logic equation for A_GT_B is
C3 & A2 & !B2

55. Magnitude Comparator A_GT_B = A3 & !B3 + C3 & A2 & !B2 + …..
+ …..
Because A3 = B3 and
A2 = B2 and
A1 > B1
i.e. C3 = 1 and C2 = 1 and
A1 & !B1 = 1
If A = 1010 and
B = 1001
is A > B?
Why?
Therefore, the next term in the
logic equation for A_GT_B is
C3 & C2 & A1 & !B1

56. Magnitude Comparator A_GT_B = A3 & !B3 + C3 & A2 & !B2
+ C3 & C2 & A1 & !B1
+ …..
Because A3 = B3 and
A2 = B2 and
A1 = B1 and
A0 > B0
i.e. C3 = 1 and C2 = 1 and
C1 = 1 and A0 & !B0 = 1
If A = 1011 and
B = 1010
is A > B?
Why?
Therefore, the last term in the
logic equation for A_GT_B is
C3 & C2 & C1 & A0 & !B0

57. Magnitude Comparator A_GT_B = A3 & !B3 + C3 & A2 & !B2
+ C3 & C2 & A1 & !B1
+ C3 & C2 & C1 & A0 & !B0

58. Magnitude Comparator Find A_LT_B A_LT_B = !A3 & B3 + C3 & !A2 & B2
+ C3 & C2 & !A1 & B1
+ C3 & C2 & C1 & !A0 & B0

59. Arithmetic Circuits: Comparator (2/3)
Let A = A3A2A1A0 , B = B3B2B1B0; xi = Ai.Bi + Ai'.Bi' A2 B2 A3 B3 A0 B0 A1 B1
(A < B)
(A > B)
(A = B) x3 x2 x1 x0
A3'.B3
A3.B3'
A3'.B3 + x3.A2'.B2
+ x3.x2.A1'.B1
+ x3. x2.x1.A0'.B0
A3.B3' + x3.A2.B2'
+ x3.x2.A1.B1'
+ x3. x2.x1.A0.B0'
x3. x2.x1.x0

60. Arithmetic Circuits: Comparator (3/3)
4-bit comp
(A < B)
(A > B)
(A = B) B3 B2 B1 B0 1
Block diagram of a 4-bit magnitude comparator