1. Genova May 2013 Diego Real – David Calvo IFIC (CSIC – Universidad de Valencia) CLBv2 1

2. KC705 XC7K325T-2FFG900C FPGA 2

3. KC705 3

4. 4

5. XC7K325T-2FFG900C FPGA Speed grade: 2 Package: FFG900 Temperature Range: C = Commercial (Tj = 0°C to +85°C) 5

6. LM32 Best at: deterministic execution configurable memory bus small and fast 1.- Open source – portable 2- Well documented 3.- White Rabbit uses it 4.- Wihsbone compatible 6

7. LM32 IMPLEMENTATION ON THE CLBv2 (fpga.vhd) 7

8. Wishbone bus Open source The Wishbone Bus is used by many designs in the OpenCores projectOpenCores The complete specifications of the bus can be found at: http://cdn.opencores.org/downloads/wbspec_b3.pdf Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels 8

9. Wishbone interconections 9

10. Wishbone on the CLBv2 (fpga.vhd) 10

11. Wishbone on the CLBv2 Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash 11

12. I2C Core 12

13. I2C Core Description I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Master Core provides an interface between a Wishbone Master and an I2C bus. It is an easy path to add I2C capabilities to any Wishbone compatible system. 13

14. I2C Core Features of the I2C Core - Compatible with Philips I2C bus standard - Multi-Master Operation - Software programmable timing - Clock stretching and wait state generation - Interrupt or bit-polling driven byte-by-byte data- transfers - Arbitration lost interrupt, with automatic transfer cancelation - (Repeated)Start/Stop signal generation/detection - Bus busy detection - Supports 7 and 10 bit addressing - Fully static and synchronous design - Fully synthesizable 14

15. I2C Core 15

16. I2C Core 16

17. I2C Core 17

18. I2C Core 18

19. I2C Core 19

20. SPI CORE 20

21. SPI CORE Description Enhanced version of the Serial Peripheral Interface available on Motorola's MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase (CPHA) and clock polarity (CPOL). The core features an 8bit wishbone interface. Very simple, very small. 21

22. SPI CORE FEATURES: Full duplex synchronous serial data transfer Variable length of transfer word up to 128 bits MSB or LSB first data transfer Rx and Tx on both rising or falling edge of serial clock independently 8 slave select lines Fully static synchronous design with one clock domain Technology independent Verilog Fully synthesizable 22

23. SPI CORE 23

24. SPI CORE 24

25. SPI CORE 25

26. SPI CORE 26

27. l TDC: DESIGN 27 Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash

28. l TDC: DESIGN 28 ISERDES OVERSAMPLE MODE

29. l Design: Technical specifications 29 Pulse Width: 8 bits 1 ns resolution Time Stamp: 32 bits 1 ns resolution 40 bits FIFO (512 elements) Tested with: o Pulse generator (18 ns rise/ fall time) o Kintex self-generated o ML605 (just two channels LVCMOS)

30. TDC: TEST ML605 LVDS Input Signal Output (48 bits) KC705 30 Well-known pattern MULTIPLEXER Ch.1 Ch.2 Ch.31 SIGNAL DISTRIBUTION Enable Interface Ch.1 Ch.31 PC

31. TDC: PATTERNS TO TEST Jitter = 0.3 ns 31 CHANNEL 1 CHANNEL 2

32. TDC: PATTERN TO TEST 32 Patterns replicated 250 times 1000 pulses x channel CHANNEL 1 CHANNEL 2

33. TDC: RESULT 33 Pulse width ns counts CHANNEL 1 ns counts CHANNEL 2

34. TDC: RESULT 34 Time between pulses ns counts CHANNEL 1 ns counts CHANNEL 2

35. TDC: Wishbone slave Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash 35

36. l 36 TDC: Wishbone slave Select an address for the core

37. l 37 TDC: Wishbone slave Create wishbone slave wishbone signals TDC core signals

38. l 38 TDC: Wishbone slave Create wishbone wrapper for our core Wishbone Wrapper Wishbone Bus Adapter Wishbone Master Core

39. l 39 TDC: Wishbone slave Create wishbone wrapper for our core Wishbone signals TDC core signals

40. l 40 TDC: Wishbone slave Wishbone adapterWishbone master core

41. l 41 TDC: Wishbone slave Core Code Wrapper Adapter Master Core

42. l 42 TDC: Wishbone slave LM32.h: Define Registers’ address LM32.h Master_core.vhd: Create Core’s registers