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1 EMCM Measurements Florian Lütticke, Martin Ritter, Felix Müller.

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Presentation on theme: "1 EMCM Measurements Florian Lütticke, Martin Ritter, Felix Müller."— Presentation transcript:

1 1 EMCM Measurements Florian Lütticke, Martin Ritter, Felix Müller

2 2 Data chain DCD ch 000...031ch 032…063 ch 224…255 DEPFET drains [0:31] 8 bits 400MBit/s DO0[1] DO0[7] DHP 32 channels multiplxed to 8-bit output DEPFET 8 buses - each bus has 8bits => 64 transfer lines between DCD and DHP Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

3 3 DCD TestPattern (hard-coded) CHDCDMSBBit6Bit5Bit4Bit3Bit2Bit1LSBDHP Ch0-127100000010 Ch1000000000128 Ch212701111111255 … Ch3012701111111128 Ch31000000000128 DCDpp Manual D is the 8+1-bit binary representation of the input current Iin. To simplify the digital data transfer, we neglect the LSB of D and transmit only 8-bit digital codes. Such a simplied code is within the range (-127, 127). We dene a current owing out of the ADC as positive 1 bus: 8 bits time Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

4 4 Sampling point adjustment L. Germic, F. Lütticke, F. Müller delay Adjustment of the DCDpp testpattern via programable delay elements For each physical link of the DHPT 1.0 a chain of delay elements are assigned with a register depth of 4 bit, such that a chain of up to 15 delay elements can be applied to the link. Each bit of the 8 bit input word can be individually delayed to ensure the highest signal integrity of the DCD DHP communication. The delays are refered to the driving clock of the signal, e.g. dcd_clk Additional to the delay of the links, the dcd_clk signal and row2_sync signal can be delayed. This will cause the dcd data conversion to be delayed and thus the the global sampling point, i.e. the sampling point of all physical input links driven by dcd_clk, will be shifted by the defined delay. Sampling points Link X Sampling position close to the transition points Sampling position at the plateau Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

5 5 Sampled test pattern Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller Reading ADU should be 128ADU (sometimes: 129ADU)

6 6 Bit Error (normalized by readings) (1) 0.001953125 = 1 wrong channel of 5120 readings Normalized to all readings (5120), sum of all channels 32 channels in 8 bits multiplexed – 1 bits gives information for 32 channels (bit0 for ch0..31)  example1: 1.6 occurs permanently in one channel, in the other sometimes  example2: 2.0 occurs permanently in two channels Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

7 7 Bit Error (normalized by readings) (2) same picture as previous, only TRUE and FALSE red: 5120x correctly readblue: wrong reading Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

8 8 Most problematic bit – bit42 Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller => GlobalDelay must be set to 0=> Adjust local delays red: 5120x correctly read blue: wrong reading (between 1 and 5120 times)

9 9 Bit Error (normalized by readings) (2) Globaldelay. 3, Localdelay: bit00:3, bit08: 2, bit 24: 3, bit 56: 3 Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller 12234556771223455677 112344567787112344567787 11234331123433 1233456512334565 MIN: 3 MIN: 15: 0 14: 0 13: 0 12: 0 11: 0 10: 0 09: 0 08: 0 07: 0 06: 1 05: 1 04: 2 03: 4 02: 3 01: 3 Max: 3 red: correctly readingblue: wrong reading

10 10 Different Gains – dynamic range Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

11 11 2bit Offset DAC (1) Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller Goal: Compensate the pedestal spread => get all the (connected) channels into the dynamic range ADU columns 2 bit Offset DAC: Compensation: 0 * IPDAC Compensation: 1/3 * IPDAC Compensation: 2/3 * IPDAC Compensation: 1 * IPDAC 1*IPDAC 1/3*IPDAC 2/3*IPDAC dynamic range

12 12 2bit Offset DAC (2) Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller Subtract current in order to get the pedestals into the dynamic range ADU columns dynamic range

13 13 Measurement method 1) Adjust pedestals (lower dynamic range) 2) Write memory into the DHP – for all pixels, there should be maximal offset dac compensation (=3) 3) Increase V/IPDAC current source 4) Wait till one reaches the upper boundary of the DCD 5) Subtract current (increase VNSubIn) in order to shift the entire distribution into the lower dynm. range 6) continue with 3) Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

14 14 V/IPDAC spread VNSubIn=41, Gain=2 Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

15 15 V/IPDAC spread VNSubIn=4, Gain=2 Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

16 16 2bit Offset DAC (3) – Offset: large spread Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller ADU columns we cannot measure since it is out of the dynamic range dynamic range VNSubIn

17 17 2bit Offset DAC (2) – VNSubIn: large spread Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller Subtract current in order to get the pedestals into the dynamic range ADU columns dynamic range VNSubIn

18 18 2bit Offset DAC - to Do - Use different gains (1,2,2,4) - How much current is equal to 1 DAC VNSubIn - Is the spread due to VNSubIn or V/IPDAC - increase current with IPAdd - Analyse delay settings for communication between DHP -> DCD Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller 2bit Offset DAC Subtraction

19 19 V/IPDAC Scan – Gain=2 Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

20 20 ADC curve Merged Software (Bonn & Munich) – available in svn @ KEK https://belle2.cc.kek.jp/svn/groups/pxdonline/epics/trunk/css/analysis https://belle2.cc.kek.jp/svn/groups/pxdonline/epics/trunk/css/dhh https://belle2.cc.kek.jp/svn/groups/pxdonline/epics/trunk/dhh/dhh_support_sw DAQ integration in python (combined in C++) - Read raw data and zero supressed - Communication via tcp (stop, start, new file, runnumber etc.) Fast ADC curve data acquisition (1 channel, ~1 second, with 10000 current steps) To do: - Analysis software/scripts for data Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

21 21 ADC curves – preliminary results Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller IPSource=70IPSource=75IPSource=80 IPSource=85IPSource=90IPSource=95 IPSource=100IPSource=105IPSource=110

22 22 ADC curves – preliminary results Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

23 23 ADC curves – preliminary results Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

24 24 ADC curves – preliminary results Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller IPSource=70IPSource=75IPSource=80 IPSource=85IPSource=90IPSource=95 IPSource=100IPSource=105IPSource=110

25 25 Outlook DHE Update: - RJ45 and Infiniband (as Hybrid7 for pilot run) and Belle II - Current source integrated on DHE 2-bit Offset DACs - Strength of V/IPDAC (too strong) - Origin of Spread - Delay settings DCD Characterization - ADC-curve: - Different gains (1,2,2,4) - RefIn, AmpLow (Voltage range?), IAmpBias, IFBPBias, IPSource, IPSource2 [nominal+-10%] - DHE current source, noise (measured, but not for fast changes (required for ADC curves)) - Internal Current source of DCD as current source (much much slower) – only few channels - Common Mode suppression - What should be measured with which dependencies? - Analysis: - Noise: integrated non-linearity (INL), differential non-linearity (DNL) - Slopes: Linear (linear range), missing codes etc. - PXD 6: - - Scan sampling point (impact of capacities in the feedback: EnCap, EnCa) Spring Test II 16.04.2015 - F. Lütticke, M.Ritter, F. Müller

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