1. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 1 CASE 2014 Technical Presentation Cycle Time and Throughput Models of Clustered Photolithography Tools for Fab-Level Simulation Kyungsu Park and James. R. Morrison Department of Industrial and Systems Engineering KAIST, South Korea

2. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 2 Presentation Overview Motivation System description: Clustered photolithography tool (CPT) Equipment models  Linear model  Affine model  Exit recursion model  Flow line model Numerical experiments  Same sample & same parameter  Different sample & same parameter  Different sample & different parameter Concluding remarks

3. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 3 Motivation

4. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 4 Motivation (1) Semiconductor manufacturing Global revenue in 2013: NT$ 9,540 billion (US$ 318 billion) Construction costs 300 mm wafer fab: NT$150 billion (US$ 5 billion [2]) 450 mm wafer fab:NT$300-450 billion (US$10-15 billion) Significant value for improvements 1996-1999: Fab production control method earned Samsung NT$ 15 bi llion (US$ 1 billion [3]) additional revenue 2005: IBM’s 30 independent supply chains merged into a single global system and saved NT$ 180 billion (US$ 6 billion [4]) … [1]

5. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 5 Motivation (2) Clustered photolithography tools (CPT) Purchase cost of NT$ 0.6-3 billion (US$ 20-100 M [5]) The most expensive tool in a fabricator Typically the bottleneck of the fabricator Key yield and cycle time contributor [5]

6. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 6 Motivation (3) Want: Models for CPTs Accurate:Predict throughput with less than 1% error Expressive:Incorporate fundamental behaviors Computationally tractable:Very quick to calculate results For the purpose of: Understanding toolset performance Enabling capacity optimization Toolset scheduling or optimization Improving the quality of fab simulation models

7. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 7 System Description: Clustered Photolithography Tool (CPT)

8. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 8 System Description: CPT (1) Multi-cluster tool, robot in each cluster, IF buffers, STK buffer Scanner is often the CPT bottleneck Largely deterministic process times Process time can vary by product Setups between lots (reticle changes, pre-scan setup, …) Wafer handling robot decision policy & deadlock prevention [6] C lustered P hotolithography T ool Scanner

9. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 9 System Description: CPT (2) “

10. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 10 System Description: Performance Metrics Notation a l : Arrival time of lot l to the tool S l : Start time of lot l in the tool C l : Completion time of lot l from the tool Performance measures Cycle time of lot l : CT l := C l - a l Lot residency time of lot l : LRT l := C l - S l Throughput time of lot l : TT l := min{ LRT l, C l – C l -1 } Lot 1 Lot 2 Lot 3 Time TT 2 TT 3 TT 1 Computation time

11. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 11 Equipment Models

12. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 12 Models for CPTs Models with various levels of detail Affine Models Exit Recursion Models Flow Line Models A(k1), B A(k1), B(k1, k2) A(k1), B(k1) With complete tool log data With wafer in/out log data With lot in/out log data Parametric flow lines Empirical flow lines Linear Model A(k1) Access Big Data Data Analytics Simulate models Detailed Model “Everything”

13. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 13 Linear Model Pros: – Simple to understand – Fast computation Cons: – Exactly matched to single wafer tool, not to CPT m AlAl Ax Model for lot cycle time in a one machine tool Wafers enter Wafers exit

14. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 14 Affine Models Referred to as the Ax+B model First wafer delay: B l Time between wafer completions: A l Process time estimation: T l PT = A k1 ∙ (w( l ) – 1) + B l ( w( l ) : the number of wafers of lot l ) B can be generalized to B(k1), B(k1, k2) Pros: Simple to understand Fast computation Cons: Only one module per process, so not matched to CPT New lots enter only when the tool is empty

15. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 15 Flow Line Models: Elementary Evolution Equations Process i W-1W

16. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 16 Flow Line Models: Extensions Elementary Evolution Equations (EEEs) can be generalized to allow: Different classes of wafer to be produced Multiple modules per process Consider robotic workload in process times of modules Consider setups – reticle setup, pre-scan setup Parameter extraction Parametric flow line model – Known process times, robot times, and setup times Empirical flow line model – Parameters extracted from tool processing data Wafers enter Wafers exit

17. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 17 Flow Line Models: Exit Recursions Theorem: Exact recursion for customer completion (exit) times [7,8] Theorem: Recursive bound for customer completion (exit) times [9] P1P1 11 …… Wafer Lots Arrive P2P2 22 PMPM MM Wafer Lots Exit … P3P3 33 …… Customers Arrive Customers Exit … R 1 =2 P2P2 R 2 =1 R 3 =3 R M =2

18. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 18 Exit Recursion Model (1) Conceptually based on flow line exit recursions Complete model No Contention at bottleneckContention at bottleneck

19. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 19 Exit Recursion Model (2) Parameter extraction Populations used as a function of available category of data

20. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 20 Model Properties Completion times in the exit recursion model exactly match those in a deterministic flow line from which the parameters are derived with (i)A single class of wafers and constant setup between wafers, or (ii)Multiple wafer classes with no setup, proportional service and geometric decay within channels Proposition: Exactness on completion times in the exit recursion model (i)All completion times in the linear model exactly match those in a single process deterministic flow line from which the parameters are derived.. (ii)Throughput time can be exactly achieved on average in a flow line with different structure.. Proposition: Exactness of completion times in the linear model (i)Completion times in the affine model exactly match those in a deterministic flow line in which each lot starts on an empty tool (via full flush constraint) from which the parameters are derived. (ii)Throughput time can be exactly achieved on average in a flow line with different structure.. Proposition: Exactness of completion times in the affine model

21. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 21 Numerical Experiments

22. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 22 Numerical Experiments LWP(Longest waiting pair) robot policy [6] : gives optimal steady state throughput Dead lock avoidance rule Setup time ~ Uniform(210, 260); Reticle alignment ~ Uniform(240, 420) 13,000 lots x 30 replications Assume detail simulation is true operation. A : Linear Model B : Affine Model - A(k1),B C : Affine Model - A(k1),B(k1) D : Affine Model - A(k1),B(k1,k2) E : FL Model F : EFL Model G : ER Model - Tool Log H : ER Model - Wafer Log I : ER Model - Lot Log [1]

23. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 23 Same Sample, Same Parameter loading level : 0.95, train level : 3, lot size : {22, 23, 24} with probability {0.25, 0.5, 0.25}, both setups 36.36%36.35%36.28%36.26% -0.09%-0.13% 2.60%3.52%3.17% --51.32%-51.33% 2.74%0.61%-2.59%2.56%2.34% 0.00%-0.00-0.01%-0.02%0.00%0.03%-0.09% -51.33% -0.00 Linear model & Affine models are only good in throughput time. ER models & Flow line models are good in all times.

24. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 24 Same Sample, Same Parameter loading level : 0.3, train level : 3, lot size : {22, 23, 24} with probability {0.25, 0.5, 0.25}, both setups 2.16%2.15% -0.30%-0.57% 2.27% 2.33% -0.04% -17.28%0.20%-0.09%0.81% 3.97% 1.71% -0.00% -0.13%-0.35%0.03%0.07%-1.82% -17.28% Linear model & Affine models are good in cycle time, and throughput time. ER models & Flow line models are good in all times

25. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 25 Different Sample, Same Parameter loading level : 0.95, train level : 3, lot size : {22, 23, 24} with probability {0.25, 0.5, 0.25}, both setups 58.35% 43.43%46.19%47.40% 4.97%-0.37%1.24%2.70%2.04% -51.40%-51.31% 2.75%0.62%-2.58%2.77%2.46% -0.12%0.05% 0.06%0.03%0.01% 0.04%-0.00% -51.31% Linear model & Affine models are only good in throughput time. ER models & Flow line models are good in all times.

26. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 26 Different Sample, Same Parameter loading level : 0.3, train level : 3, lot size : {22, 23, 24} with probability {0.25, 0.5, 0.25}, both setups 2.57%2.65%2.52%2.42% -0.17%-0.35% 2.30%2.28% 0.44% -17.22% 0.29%-0.03%0.84% 3.98% 2.23% 0.09%0.19%0.17% -0.16%-0.37%0.05%0.14%-1.46% -17.14%-17.16% Linear model & Affine models are good in cycle time, and throughput time. ER models & Flow line models are good in all times

27. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 27 Different Sample, Different Parameter From loading level : 0.95 & train level : 3, To lading level : 0.8 & train level : 1 With lot size : {22, 23, 24} with probability {0.25, 0.5, 0.25}, both setups -5.09%-4.05% -5.90% -4.12%-0.04% 0.43% 19.29% 20.21% 17.67% -37.96% 0.11%0.08%2.17%6.36%5.67% -5.19%-5.09% -4.97%-0.00%-0.11%0.00%-0.04% -0.42% -37.89% -37.81% Linear model & Affine models are slightly good in cycle time, and throughput time. ER models are good in lot residency time, and throughput time. Only FL models are good in all times.

28. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 28 Different Sample, Different Parameter From lot size: {22, 23, 24} with {0.25, 0.5, 0.25}, to lot size: {12, 13, 14} with {0.25, 0.5, 0.25} with loading level : 0.95, train level : 3, both setups -33.18%-14.54%-15.85%-15.21%0.29%-0.64% 17.66%16.71% -0.43% -59.70%-56.67%-56.68%-56.67%1.26%0.39% 3.56%7.43% 0.38% -16.21% -9.92% -0.13%-0.16% -0.17% 0.02% -3.78% Linear model & Affine models are bad in all times. ER models are good in lot residency time, and throughput time. Only FL models are good in all times.

29. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 29 Computational Comparison Relative Computation Time Linear Model0.5 Affine Model1 ER Model2.4 FL Model120 Detailed Simulation13,000

30. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 30 Accuracy Comparison Errors relative to detailed model Error of 20%+ Error 5-20% Error 0-5% Same Sample, Same ParameterDifferent Sample, Same ParameterDifferent Sample, Different Parameter Linear ModelCTLRTTTCTLRTTTCTLRTTT Affine ModelsCTLRTTTCTLRTTTCTLRTTT ER ModelsCTLRTTTCTLRTTTCTLRTTT Flow Line ModelsCTLRTTTCTLRTTTCTLRTTT

31. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 31 Concluding Remarks

32. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 32 Concluding Remarks CPT: Expensive & typically fab bottleneck toolset Models for CPT throughput time, process time & cycle time Classic models: Linear, affine Recent models: Flow line, exit recursion Compare: Computation and accuracy Next directions Improved models: Newer exit recursions, additional parameters Implementation: Fab simulation, optimization, etc.

33. © 2014 – James R. Morrison – IEEE CASE – August 2014 - 33 References 1.HIS iSuppli April 2011 2.Elpida Memory, Inc., available at http://www.eplida.com, 3.Leachman, Robert C., Jeenyoung Kang, and Vincent Lin. "SLIM: Short cycle time and low inventory in manuf acturing at samsung electronics." Interfaces32.1 (2002): 61-77 4.http://www.forbes.com/forbes/2003/0811/076.html 5.Roger H. French and V. Hoang, “Immersion Lithography: Photomask and Wafer-Level Materials,” Tran. Annual Review of Materials Research, Vol. 39, 93-126 6.Hyun Joong Yoon and Doo Yong Lee, “Deadlock-free scheduling of photolithography equipment in semicon ductor fabrication,” IEEE Trans. Semi. Mfg., vol. 17, no. 1, pp. 42-54, 2004 7.Avi-Itzhak, B. "A sequence of service stations with arbitrary input and regular service times." Management Science 11.5 (1965): 565-571 8.Friedman, Henry D. "Reduction methods for tandem queuing systems." Operations Research 13.1 (1965): 1 21-131 9.Park, Kyungsu, and James R. Morrison. "Performance evaluation of deterministic flow lines: Redundant mo dules and application to semiconductor manufacturing equipment." Automation Science and Engineering ( CASE), 2010 IEEE Conference on. IEEE, 2010 10.Morrison, James R. "Deterministic flow lines with applications." Automation Science and Engineering, IEEE Transactions on 7.2 (2010): 228-239 11.Morrison, James R. "Multiclass flow line models of semiconductor manufacturing equipment for fab-level s imulation." Automation Science and Engineering, IEEE Transactions on 8.1 (2011): 81-94 Longest waiting pair: [7] Geismar, H.N.; Sriskandarajah, C.; Ramanan, N., "Increasing throughput for robotic cells with parallel Machines and multiple robots," IEEE Trans. Auto. Sci. and Eng., vol.1, no.1, pp.84,89, Jul 2004