1. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 1 Models for the Performance of Clustered Photolithography Tools with Applications James R. Morrison Associate Professor Industrial & Systems Engineering

2. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 2 Presentation Overview Motivation System description (CPT) Models for CPTs Some recent flow line theory Application opportunities Where next? Concluding remarks C lustered Photolithography T ool Linear Affine (Ax+B) Flow line Detailed Exact decomposition Exit recursions Markovian models Capacity increase Toolset agility Fab simulation components Industry interaction Next development steps

3. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 3 Acknowledgements Much of the work discussed here was developed with – Dr. Kyungsu Park – Dr. Woo-sung Kim – MS student John Park – BS student Hyunsuk Baek Several of the slides were prepared by – Dr. Kyungsu Park – Dr. Woo-sung Kim – MS student John Park – BS student Hyunsuk Baek

4. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 4 Presentation Overview Motivation System description (CPT) Models for CPTs Some recent flow line theory Application opportunities Where next? Concluding remarks

5. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 5 Motivation (1) Semiconductor manufacturing – Global revenue in 2013: NT$ 9,540 billion (US$ 318 billion) Construction costs – 300 mm wafer fab: NT$150 billion (US$ 5 billion [2]) – 450 mm wafer fab:NT$300-450 billion (US$10-15 billion) Significant value for improvements – 1996-1999: Fab production control method earned Samsung NT$ 15 billion (US$ 1 billion [3]) additional revenue – 2005: IBM’s 30 independent supply chains merged into a single global system and saved NT$ 180 billion (US$ 6 billion [4]) –…–… [1]

6. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 6 Motivation (2) Clustered photolithography tools (CPT) – Purchase cost of NT$ 0.6-3 billion (US$ 20-100 M [5]) – The most expensive tool in a fabricator – Typically the bottleneck of the fabricator – Key yield and cycle time contributor [5]

7. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 7 Motivation (3) CPT Vendor: “Our CPTs can run at 120 wph” Fab analyst: “Your CPTs can run at 80 wph”  Who is right?Exhaustive and exhausting tool log analysis… CPT Vendor: “Our CPTs are awesome” Fab analyst: “We are disappointed” 

8. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 8 Motivation (4) Want: Models for CPTs – Accurate:Predict throughput with less than 1% error – Expressive:Incorporate fundamental behaviors – Computationally tractable:Very quick to calculate results For the purpose of: – Understanding toolset performance – Enabling capacity optimization – Toolset scheduling or optimization – Improving the quality of fab simulation models Discuss in the application section

9. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 9 Presentation Overview Motivation System description (CPT) Models for CPTs Some recent flow line theory Application opportunities Where next? Concluding remarks

10. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 10 System Description: CPT (1) Multi-cluster tool, robot in each cluster, IF buffers, STK buffer Scanner is often the CPT bottleneck Largely deterministic process times Process time can vary by product Setups between lots (reticle changes, pre-scan setup, …) Wafer handling robot decision policy & deadlock prevention C lustered P hotolithography T ool Scanner [6]

11. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 11 System Description: CPT (2) P1 P2 P6 … buffer … … P11 Wafers Enter Wafers Exit Pre-scan processes Post-scan processes Scanner Conceptual diagram of a CPT (robots “removed”)

12. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 12 System Description: Performance Metrics Notation – a l : arrival time of lot l to the tool queue – S l : start time of lot l on a tool – C l : completion time of lot l on a tool – W l : wafers in lot l Performance measures – Cycle time of lot l : T l CT := C l - a l – Process time of lot l : T l PT := C l - S l – Throughput time of lot l : T l TT := min{ T l PT, C l – C l -1 } Lot 1 Lot 2 Lot 3 Time T 2 TT T 3 TT T 1 TT Computation time

13. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 13 Presentation Overview Motivation System description (CPT) Models for CPTs Some recent flow line theory Application opportunities Where next? Concluding remarks

14. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 14 Models for CPTs Models with various levels of detail Affine Models Exit Recursion Models Flow Line Models A(k1), B A(k1), B(k1, k2) A(k1), B(k1) With complete tool log data With wafer in/out log data With lot in/out log data Parametric flow lines Empirical flow lines Collect Tool Log Data Train a set of parameters Simulate models Linear Model A(k1) Detailed Model “Everything”

15. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 15 Linear Model Pros: – Simple to understand – Fast computation Cons: – Exactly matched to single wafer tool, not to CPT m AlAl Ax Model for lot cycle time in a one machine tool Wafers enter Wafers exit

16. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 16 Affine Models – Referred to as the Ax+B model – First wafer delay: B l – Time between wafer completions: A l – Process time estimation: T l PT = A k1 ∙ (w( l ) – 1) + B l ( w( l ) : the number of wafers of lot l ) B can be generalized to B(k1), B(k1, k2) Pros: Simple to understand Fast computation Cons: Only one module per process, so not matched to CPT New lots enter only when the tool is empty

17. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 17 Flow Line Models – Elementary Evolution Equations Process i W-1W

18. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 18 Flow Line Models Elementary Evolution Equations (EEEs) can be generalized to allow: – Different classes of wafer to be produced – Multiple modules per process – Consider robotic workload in process times of modules – Consider setups – reticle setup, pre-scan setup Parameter extraction – Parametric flow line model – Known process times, robot times, and setup times – Empirical flow line model – Parameters extracted from wafer advancement data Wafers enter Wafers exit

19. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 19 Exit Recursion Model (1) Extend affine models to allow for flow line style behaviors Idea: – Bottleneck analysis approach – Obtain parameters from limited population – Example For only wafer or lot in/out log data, – Restrict population to account for desired parameter meaning – Least square method (LSM) to obtain parameters No Contention at bottleneckContention at bottleneck

20. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 20 Exit Recursion Model (2) where

21. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 21 Exit Recursion Model (3)

22. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 22 Computational Comparison Relative Computation Time Linear Model0.5 Affine Model1 ER Model2.4 FL Model120 Detailed Simulation13,000

23. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 23 Accuracy Assessment Errors relative to detailed model – Error of 20%+ – Error 5-20% – Error 0-5% Different Sample & Different Parameter Linear ModelCTPTTT Affine ModelsCTPTTT ER ModelsCTPTTT Flow Line ModelsCTPTTT

24. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 24 Presentation Overview Motivation System description (CPT) Models for CPTs Some recent flow line theory Application opportunities Where next? Concluding remarks

25. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 25 Some Recent Flow Line Theory (1): Exit Recursions Exit recursions describe wafer flow using a single equation Avi-Itzhak, Friedman in 1965 ([7, 8]) – Random customer arrivals and deterministic service times Theorem: Exact recursion for customer completion (exit) times – c M (k) is the completion time of wafer k from process M – a K is the arrival time of wafer k to the system –  B is the bottleneck process time P1P1 11 …… Wafer Lots Arrive P2P2 22 PMPM MM Wafer Lots Exit … P3P3 33

26. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 26 Some Recent Flow Line Theory (2): Exit Recursions Multiple servers per process in 2010 ([9]) Theorem: Recursive bound for customer completion (exit) times –  (i) max is the bottleneck process time for those processes with i servers – Conjecture that this is an exact result P1P1 11 …… Customers Arrive 22 MM Customers Exit … 33 R 1 =2 P2P2 R 2 =1 P3P3 R 3 =3 PMPM R M =2

27. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 27 Some Recent Flow Line Theory (3): Exact Decompositions Theorem: Exact channel decomposition in 2010, 2011 ([10, 11]) Theorem: Can be modeled as a Markov chain in 2014 ([12]) Theorem: Systems with setups (as in semiconductor manufacturing) can be modeled and optimized in 2014 ([13]) P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 P8P8 P9P9 P 10 P 11 11 44 66  10 22 33 55 77 88 99  11 Channel 1Channel 2Channel 3

28. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 28 Presentation Overview Motivation System description (CPT) Models for CPTs Some recent flow line theory Application opportunities Where next? Concluding remarks Capacity increase Toolset agility Fab modeling components

29. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 29 Application Opportunities: Capacity Increase Fundamental process/robot bottleneck analysis & mitigation More complicated analysis – Buffer size implications – Manufacturing environment & mitigation – Penultimate dominating process P1 P2 P6 … buffer … … P11 Wafers Enter Wafers Exit Pre-scan processes Post-scan processes Scanner Fab initiative: Aggressive pursuit of CPT wph results in 20% capacity improvement

30. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 30 Application Opportunities: Toolset Agility Wafers are commonly admitted to a CPT as soon as possible – Deployment opportunity of the lot is reduced – High priority hot lots experience additional queueing – Lot/wafer residency time and buffer level greater than required Question: When should wafers be admitted to the CPT? – Maintain throughput capacity – Minimize residency time and thereby increase agility

31. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 31 Application Opportunities: Toolset Agility (2) Lexicographic Multi-Objective Linear Program (LMOLP) ([14])

32. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 32 Application Opportunities: Toolset Agility (3) Results: Detailed CPT model Trade-off between throughput and wafer residency time JIT

33. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 33 Application Opportunities: Fab Simulation/Modeling Equipment and fabricator simulations are used to – Predict value of changes to fabricator capacity – Predict value of changes to fabricator production control policies – Predict capacity of fabricators Want expressive, accurate and computationally tractable models to help make decisions on US$ billions – Future manufacturing facilities will cost US$15 billion – High quality models enable improved decisions

34. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 34 Application Opportunities: Fab Optimization Can also be used for model based optimization – Local toolset production control – Global fab production control

35. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 35 Presentation Overview Motivation System description (CPT) Models for CPTs Some recent flow line theory Application opportunities Where next? Concluding remarks

36. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 36 Where next? Industry application – Model based CPT capacity optimization – Toolset agility improvement via judicious CPT wafer release – Improved fab simulation models – Incorporation of improved models into fab scheduling Model development – Flow line theories – Improved Exit Recursion models – Analytic methods for CPT capacity optimization

37. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 37 Presentation Overview Motivation System description (CPT) Models for CPTs Some recent flow line theory Application opportunities Where next? Concluding remarks

38. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 38 Concluding Remarks How to understand clustered photolithography tools? Models for CPTs – Linear/Affine – Flow line based Some recent flow line theory Application opportunities Can these models be used to help improve real fab performance?

39. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 39 Models for the Throughput of Clustered Photolithography Tools with Applications James R. Morrison Email: james.morrison@kaist.edu Homepage: http://xS3D.kaist.edu

40. ©2014 –James R. Morrison – ISMI Keynote II – August 17, 2014 – 40 References 1.HIS iSuppli April 2011 2.Elpida Memory, Inc., available at http://www.eplida.com, 3.Leachman, Robert C., Jeenyoung Kang, and Vincent Lin. "SLIM: Short cycle time and low inventory in manufacturing at samsung electronics." Interfaces32.1 (2002): 61-77 4.http://www.forbes.com/forbes/2003/0811/076.html 5.Roger H. French and V. Hoang, “Immersion Lithography: Photomask and Wafer-Level Materials,” Tran. Annual Review of Materials Research, Vol. 39, 93-126 6.Hyun Joong Yoon and Doo Yong Lee, “Deadlock-free scheduling of photolithography equipment in semiconductor fabrication,” IEEE Trans. Semi. Mfg., vol. 17, no. 1, pp. 42-54, 2004 7.Avi-Itzhak, B. "A sequence of service stations with arbitrary input and regular service times." Management Science 11.5 (1965): 565-571 8.Friedman, Henry D. "Reduction methods for tandem queuing systems." Operations Research 13.1 (1965): 121-131 9.Park, Kyungsu, and James R. Morrison. "Performance evaluation of deterministic flow lines: Redundant modules and application to semiconductor manufacturing equipment." Automation Science and Engineering (CASE), 2010 IEEE Conference on. IEEE, 2010 10.Morrison, James R. "Deterministic flow lines with applications." Automation Science and Engineering, IEEE Transactions on 7.2 (2010): 228-239 11.Morrison, James R. "Multiclass flow line models of semiconductor manufacturing equipment for fab-level simulation." Automation Science and Engineering, IEEE Transactions on 8.1 (2011): 81-94 12.Kim, Woo-sung, and James R. Morrison, “On the steady state behavior of deterministic flow lines with random arrivals.” Accepted June 14, 2014 for IEEE Transactions on Automation Science and Engineering (IEEE) 13.Kim, Woo-sung and James R. Morrison, “The throughput rate of serial production lines with regular process times and random setups: Markovian models and applications to semiconductor manufacturing,” Computers & Operations Research (Elsevier), Online at http://dx.doi.org/10.1016/j.cor.2014.03.022, April 4, 2014. 14.Park, Kyungsu and James R. Morrison, “Controlled wafer release in clustered photolithography tools: Flexible flow line job release scheduling and an LMOLP heuristic,” IEEE Transactions on Automation Science and Engineering (IEEE), Online at http://dx.doi.org/10.1109/TASE.2014.2311997, April 7, 2014. Longest waiting pair: [7] Geismar, H.N.; Sriskandarajah, C.; Ramanan, N., "Increasing throughput for robotic cells with parallel Machines and multiple robots," IEEE Trans. Auto. Sci. and Eng., vol.1, no.1, pp.84,89, Jul 2004