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Digitaalsüsteemide verifitseerimise kursus1 Exercises Binary decision diagrams ROBDD generation. Shannon expansion Finding an optimal ordering Dynamic.

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Presentation on theme: "Digitaalsüsteemide verifitseerimise kursus1 Exercises Binary decision diagrams ROBDD generation. Shannon expansion Finding an optimal ordering Dynamic."— Presentation transcript:

1 Digitaalsüsteemide verifitseerimise kursus1 Exercises Binary decision diagrams ROBDD generation. Shannon expansion Finding an optimal ordering Dynamic node reordering SAT Creating the SAT instance: characteristic formula SAT solving

2 Digitaalsüsteemide verifitseerimise kursus 2 Exercises Equivalence checking Using ROBDDs Using SAT Code Coverage Generate minimal tests for 100% statement, branch and path coverage Assertions Evaluate operations on SVA sequences

3 Digitaalsüsteemide verifitseerimise kursus3 Binary decision diagrams ROBDD generation. Shannon expansion f = ¬a¬bcd + a¬bc + ¬abc + abc + ab¬cd + a¬b¬cd 1) Generate the binary decision tree 2) Reduce it to an ROBDD 3) Derive the function from the BDD

4 Digitaalsüsteemide verifitseerimise kursus4 Binary decision diagrams ROBDD generation. Find the optimal ordering f = ab + a¬b¬c¬d + a¬bcd + ¬abc + ¬ab¬cd + ¬a¬bcd Reorder dynamically the 2. and 3. variable

5 Digitaalsüsteemide verifitseerimise kursus5 SAT Create a characteristic formula for f = ¬ac + b¬c + a¬b

6 Digitaalsüsteemide verifitseerimise kursus6 Equivalence checking Whether f and g are equivalent? f = ¬ac + b¬c + a¬b g = a¬c + ¬bc + ¬ab 1) Check with SAT 2) Check with ROBDDs

7 Digitaalsüsteemide verifitseerimise kursus7 Code Coverage void Function(int x,y,z,w) { int a, b, c; a=0; if(x) { a = 1;} else { if(a==0) { a = 1;} else { a = a + 1;} } if(y) { if(z) { a = 2;} } if(w) { b=c;} } 1) Generate the minimum test for the full statement coverage (inputs w, x, y & z) 2) Generate the minimum test for the full branch coverage 3) Generate the minimum test for the full path coverage 4) Which statements/branches are unreachable (i.e. dead code)?

8 Digitaalsüsteemide verifitseerimise kursus8 Assertions 1) When is a sequence S1|=>S2 true? S1=##1INT ##[0,3] TASK; S2=HDLR ##[1,4] DONE a) b) c)


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