1. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2010 Linear Programming – A Mathematical Optimization Technique Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html

2. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)2 What is Linear Programming   Linear programming (LP) is a mathematical method for selecting the best solution from the available solutions of a problem.   Method:   State the problem and define variables whose values will be determined.   Develop a linear programming model:   Write the problem as an optimization formula (a linear expression to be minimized or maximized)   Write a set of linear constraints   An available LP solver (computer program) gives the values of variables.

3. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)3 Types of LPs   LP – all variables are real.   ILP – all variables are integers.   MILP – some variables are integers, others are real.   A reference:   S. I. Gass, An Illustrated Guide to Linear Programming, New York: Dover, 1990.

4. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)4 A Single-Variable Problem   Consider variable x   Problem: find the maximum value of x subject to constraint, 0 ≤ x ≤ 15.   Solution: x = 15. 0 15 Constraint satisfied x Solution x = 15

5. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)5 Single Variable Problem (Cont.)   Consider more complex constraints:   Maximize x, subject to following constraints:   x ≥ 0(1)   5x ≤ 75(2)   6x ≤ 30(3)   x ≤ 10(4) 051015x (1) (2) (3) (4) All constraints satisfied Solution, x = 5

6. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)6 A Two-Variable Problem   Manufacture of chairs and tables:   Resources available:   Material: 400 boards of wood   Labor: 450 man-hours   Profit:   Chair: $45   Table: $80   Resources needed:   Chair   5 boards of wood   10 man-hours   Table   20 boards of wood   15 man-hours   Problem: How many chairs and how many tables should be manufactured to maximize the total profit?

7. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)7 Formulating Two-Variable Problem   Manufacture x 1 chairs and x 2 tables to maximize profit: P = 45x 1 + 80x 2 dollars   Subject to given resource constraints:   400 boards of wood,5x 1 + 20x 2 ≤ 400(1)   450 man-hours of labor,10x 1 + 15x 2 ≤ 450(2)   x 1 ≥ 0(3)   x 2 ≥ 0 (4)

8. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)8 Solution: Two-Variable Problem Chairs, x 1 Tables, x 2 (1) (2) 0 10 20 30 40 50 60 70 80 90 40 30 20 10 0 (24, 14) Profit increasing decresing P = 2200 P = 0 Best solution: 24 chairs, 14 tables Profit = 45×24 + 80×14 = 2200 dollars (3) (4) Material constraint Man-power constraint

9. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)9 Change Profit of Chair to $64/Unit   Manufacture x 1 chairs and x 2 tables to maximize profit: P = 64x 1 + 80x 2 dollars   Subject to given resource constraints:   400 boards of wood,5x 1 + 20x 2 ≤ 400(1)   450 man-hours of labor,10x 1 + 15x 2 ≤ 450(2)   x 1 ≥ 0(3)   x 2 ≥ 0 (4)

10. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)10 Solution: $64 Profit/Chair Chairs, x 1 Tables, x 2 (1) (2) Profit increasing decresing P = 2880 P = 0 Best solution: 45 chairs, 0 tables Profit = 64×45 + 80×0 = 2880 dollars 0 10 20 30 40 50 60 70 80 90 (24, 14) 40 30 20 10 0 (3) (4) Material constraint Man-power constraint

11. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)11 A Dual Problem   Explore an alternative.   Questions:   Should we make tables and chairs?   Or, auction off the available resources?   To answer this question we need to know:   What is the minimum price for the resources that will provide us with same amount of revenue from sale as the profits from tables and chairs?   This is the dual of the original problem.

12. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)12 Formulating the Dual Problem   Revenue received by selling off resources:   For each board, w 1   For each man-hour, w 2   Minimize 400w 1 + 450w 2   Subject to constraints:   5w 1 + 10w 2 ≥ 45   20w 1 + 15w 2 ≥ 80   w 1 ≥ 0   w 2 ≥ 0 Resources: Material: 400 boards Labor: 450 man-hrs Profit: Chair: $45 Table: $80 Resources needed: Chair 5 boards of wood 10 man-hours Table 20 boards of wood 15 man-hours

13. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)13 The Duality Theorem  If the primal has a finite optimum solution, so does the dual, and the optimum values of the objective functions are equal.  Reference: G. Strang, Linear Algebra and Its Applications. Fort Worth: Harcourt Brace Javanovich College Publishers, third edition, 1988.

14. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)14 Primal-Dual Problems   Primal problem   Fixed resources   Maximize profit   Variables:   x 1 (number of chairs)   x 2 (number of tables)   Maximize profit 45x 1 +80x 2   Subject to:   5x 1 + 20x 2 ≤ 400   10x 1 + 15x 2 ≤ 450   x 1 ≥ 0   x 2 ≥ 0   Solution:   x 1 = 24 chairs, x 2 = 14 tables   Profit = $2200   Dual Problem  Fixed profit  Minimize value   Variables:  w 1 ($ value/board of wood)  w 2 ($ value/man-hour)   Minimize value 400w 1 +450w 2   Subject to:  5w 1 + 10w 2 ≥ 45  20w 1 + 15w 2 ≥ 80  w 1 ≥ 0  w 2 ≥ 0   Solution:  w 1 = $1, w 2 = $4  value = $2200

15. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)15 LP for n Variables n minimize Σ cj xjObjective function j =1 n subject to Σ aij xj ≤ bi, i = 1, 2,..., m j =1 n Σ cij xj = di, i = 1, 2,..., p j =1 Variables: xj Constants: cj, aij, bi, cij, di

16. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)16 Algorithms for Solving LP  Simplex method  G. B. Dantzig, Linear Programming and Extension, Princeton, New Jersey, Princeton University Press, 1963.  Ellipsoid method  L. G. Khachiyan, “A Polynomial Algorithm for Linear Programming,” Soviet Math. Dokl., vol. 20, pp. 191-194, 1984.  Interior-point method  N. K. Karmarkar, “A New Polynomial-Time Algorithm for Linear Programming,” Combinatorica, vol. 4, pp. 373-395, 1984.  Course website of Prof. Lieven Vandenberghe (UCLA), http://www.ee.ucla.edu/ee236a/ee236a.html http://www.ee.ucla.edu/ee236a/ee236a.html

17. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)17 Basic Ideas of Solution methods Constraints Extreme points Objective function Constraints Extreme points Objective function Simplex: search on extreme points. Complexity: polynomial in n, number of variables Interior-point methods: Successively iterate with interior spaces of analytic convex boundaries. Complexity: O(n 3.5 L), L = no. of int. values

18. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)18 Integer Linear Programming (ILP)  Variables are integers.  Complexity is exponential – higher than LP.  LP relaxation  Convert all variables to real, preserve ranges.  LP solution provides guidance.  Rounding LP solution can provide a non-optimal solution.

19. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)19 Traveling Salesperson Problem (TSP) 1 3 2 5 4 12 27 18 10 5 20 12 15 19 6

20. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)20 Solving TSP: Five Cities Distances (dij) in miles (symmetric TSP, general TSP is asymmetric) City j=1 j=1 j=2 j=2j=3j=4j=5 i=1 i=1018101227 i=2 i=218051220 i=3 i=310501519 i=4 i=412121506 i=5 i=527201960

21. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)21 Search Space: No. of Tours  Asymmetric TSP tours  Five-city problem: 4 × 3 × 2 × 1 = 24 tours  Ten-city problem: 362,880 tours  15-city problem: 87,178,291,200 tours  50-city problem: 49! = 6.08×10 tours  50-city problem: 49! = 6.08×10 62 tours Time for enumerative search assuming 1 μs per tour evaluation=1.93×10 years Time for enumerative search assuming 1 μs per tour evaluation=1.93×10 55 years

22. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)22 A Greedy Heuristic Solution City j = 1 j = 2j = 3j = 4j = 5 i = 1 (start) 018101227 i = 218051220 i = 310501519 i = 412 1506 i = 527201960 Tour length = 10 + 5 + 12 + 6 + 27 = 60 miles (non-optimal)

23. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)23 ILP Variables, Constants and Constraints 1 3 2 5 4 d14 = 12 d15 = 27 d12 = 18 d13 = 10 x14 ε [0,1] x15 ε [0,1] x12 ε [0,1] x13 ε [0,1] x12 + x13 + x14 + x15 = 1 four other similar equations Integer variables: xij = 1, travel i to j xij = 0, do not travel i to j Real constants: dij = distance from i to j

24. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)24 Objective Function and ILP Solution 5 i - 1 Minimize ∑ ∑ xij × dij i = 1 j = 1 xij xij j=1 j=12345 i=1 i=100100 210000 301000 400001 500010 ∑ xij = 1 for all i j ≠ i

25. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)25 ILP Solution 1 3 2 5 4 d13 = 10 d45 = 6 Total length = 45 but not a single tour d54 = 6 d21 = 18 d32 = 5

26. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)26 Additional Constraints for Single Tour  Following constraints prevent split tours. For any subset S of cities, the tour must enter and exit that subset: ∑ xij ≥ 2 for all S, |S| < 5 i ε S j ε S Any subset Remaining set At least two arrows must cross this boundary.

27. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)27 ILP Solution 1 3 2 5 4 d13 = 10 d41 = 12 Total length = 53 d54 = 6 d25 = 20 d32 = 5

28. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)28 ILP Example: Test Minimization  A combinational circuit has n test vectors that detect m faults. Each vector detects a subset of faults. Find the smallest subset of test vectors that each fault is detected by at least N vectors.  Simulate vectors without dropping faults. T1T2..Tj...Tn F1100110100 F2001100010.................... Fj100110011.......... Fm011100001 Faults Test vectors fij = 1, if test Ti detects fault Fj

29. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)29 Test Minimization by ILP n minimize Σ ti Objective function i=1 n subject to Σ fij ti ≥ N, j = 1, 2,..., m i=1 Construct an ILP model: 1.Assign an integer variable ti ε [0,1] to ith test vector such that ti = 1, if we select ti, otherwise ti= 0. 2.Define an integer constant fij ε [0,1] such that fij = 1, if ith vector detects jth fault, otherwise fij = 0. Values of constants fij are determined by fault simulation.

30. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)30 N-Detect Tests (N = 5) Circuit Unoptimized vectors ILP (exact) Minimum vectors CPU s c432 c4326081971.0 c499 c4993792602.3 c880 c8801,023127881.8 c1355 c13557554204.4 c1908 c19081,0555436.9 c2670 c26709594777.2 c3540 c35401,97147120008.5 c5315 c53151,07937640.7 c6288 c62882435734740.0 c7552 c75522,165841114.3

31. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)31 Why ILP Solution is Exponential? LP solution found in polynomial time (bound on ILP solution) Must try all 2 n roundoff points First variable Second variable Constraints Objective (maximize)

32. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)32 Characteristics of ILP  Worst-case complexity is exponential in number of variables.  Linear programming (LP) relaxation, where integer variables are treated as real, gives a lower bound on the objective function.  Recursive rounding of relaxed LP solution to nearest integers gives an approximate solution to the ILP problem.  K. R. Kantipudi and V. D. Agrawal, “A Reduced Complexity Algorithm for Minimizing N-Detect Tests,” Proc. 20 th International Conf. VLSI Design, January 2007, pp. 492-497.

33. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)33 Recursive Rounding Algorithm 1.Obtain a relaxed LP solution. if each variable in the solution is an integer. 1.Obtain a relaxed LP solution. Stop if each variable in the solution is an integer. 2.Round the variable closest to an integer. 3.Remove any constraints that are now unconditionally satisfied. 4.Go to step 1.

34. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)34 Complexity of Approximation  Recursive rounding:  ILP is transformed into k LPs with progressively reducing number of variables, where k is the size of the solution.  A solution that satisfies all constraints is guaranteed; this solution is often close to optimal.  Number of LPs, k, is the size of the final solution, i.e., the number of non-zero variables in the test minimization problem.  Recursive rounding complexity is k × O(n p ), where k ≤ n, n is number of variables.

35. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)35 Four-Bit ALU Circuit Initial vectors ILP Recursive rounding Vectors CPU s Vectors 285140.65140.42 400131.07131.00 500124.38133.00 1,000124.17123.00 5,0001212.95129.00 10,0001234.611217.0 16,3841287.471237.0

36. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)36 ILP vs. Recursive Rounding 0 5,000 10,000 15,000 Vectors 100 75 50 25 0 ILP Recursive Rounding CPU s

37. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)37 N-Detect Tests (N = 5) Circuit Unoptimized vectors Relaxed LP/Recur. rounding ILP (exact) Lower bound Min. vectors CPU s Min. vectors CPU s c432 c432608196.381971.01971.0 c499 c499379260.002601.22602.3 c880 c8801,023125.9712814.0127881.8 c1355 c1355755420.004203.24204.4 c1908 c19081,055543.005434.65436.9 c2670 c2670959477.004774.74777.2 c3540 c35401,971467.2547772.047120008.5 c5315 c53151,079374.3337718.037640.7 c6288 c628824352.525739.05734740.0 c7552 c75522,165841.0084152.0841114.3

38. A Primal-Dual Solution (N = 1) Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)38 Circuit Name Lower bound on vectors Recursive LP minimizationPrimal-dual minimization Unopt. vectors LP CPU s Minimized vectors Unopt. vectors Total CPU s Minimized vectors c432276082.00369835.5231 c499523791.00522211.3552 c88013102331.00281008227.2125 c1355847555.00845071.9584 c190810610558.001077282.50107 c2670449599.0084103917.4179 c3540781971197.001052042276.9195 c5315371079464.00721117524.5367 c6288624378.0018258218.917 c7552652165151.00145201671.21139 M. A. Shukoor and V. D. Agrawal, “A Primal-Dual Solution to Minimal Test Generation Problem,” Proc. 12 th IEEE VLSI Design & Test Symp. (VDAT08), 2008, pp. 269-279.

39. Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)39 Finding LP/ILP Solvers  R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco, California: Scientific Press, 1993. Several of programs described in this book are available to Auburn users.  B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and Experienced Users, Cambridge University Press, 2006.  Search the web. Many programs with small number of variables can be downloaded free.

40. A Circuit Optimization Problem  Given:  Circuit netlist  Cell library with multiple versions for each cell  Select cell versions to optimize a specified characteristic of the circuit. Typical characteristics are:  Area  Power  Delay Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)40

41. Example: Cell(X), X = 0 or 1  X = 0  Delay = d  Power = 3 × p  X = 1  Delay = 2 × d  Power = 0.5 × p  Cell delay = (1 – X) d + 2 X d  Power = 3(1 – X) p + 0.5 X p Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)41

42. ILP Model: Minimum Power & Delay  Ti = signal arrival time at ith input; Ti = 0 for all PIs  Tk = signal arrival time at cell output  Tk ≥ Ti + (1 – Xk) dk + 2 Xk dk, for all i Where, dk = nominal delay of gate Xk = 0 or 1, specifies version of cell Minimize α TPO + ∑ [3(1 – Xk) pk + 0.5 Xk pk]α is constant all k all k Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)42 kth Cell Arrival time = Tk Arrival time = T1 Ti

43. Given Clock Specification  Tj = 0, for all primary inputs j  Tk ≤ clock period, for all primary outputs k  Tk ≥ Ti + (1 – Xk) dk + 2 Xk dk, for all gates k with input i Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)43 Combinational Logic Register Clock

44. Minimum Power Design  Minimize ∑ 3(1 – Xk) pk + 0.5 Xk pk all k wherepk = nominal power consumption of kth cell Spring 2010, Feb 22...ELEC 7770: Advanced VLSI Design (Agrawal)44

45. Logic Minimization  Consider a four-variable function, {2,4,6,8,9,10,12,13,15}  Karnaugh map shows prime implicants (PI) found by Quine-McCluskey procedure.  Find the minimum number of Pis to cover all minterms. Fall 2008, Oct 13...ELEC2200-002 Lecture 545 111 11 1 111 A B C D EPI’s Non-EPI’s

46. Select a Minimal Set of PI’s Covered by EPI →xxxxx Minterm →2468910121315 PI1xxxx PI2xx PI3xx PI4xx PI5xx PI6xx PI7xx Fall 2008, Oct 13...ELEC2200-002 Lecture 546 1.First select essential prime implicants (EPIs). 2.Cover remaining minterms with smallest number of prime implicants (Pis).

47. Cover Remaining Minterms Remaining minterms →24610 PI2xx PI3xx PI4xx PI5x PI6x Fall 2008, Oct 13...ELEC2200-002 Lecture 547 Integer linear program (ILP): Define integer {0,1} variables, xk = 1, select PIk; xk = 0, do not select PIk. Minimize  k xk, subject to following constraints: x2 + x3 ≥ 1(cover minterm 2) x4 + x5 ≥ 1(cover minterm 4) x2 + x4 ≥ 1(cover minterm 6) x3 + x6 ≥ 1(cover minterm 10) A solution is x3 = x4 = 1, x2 = x5 = x6 = 0

48. Minimized Function  F(A,B,C,D) =PI1 + PI3 + PI4 + PI7 =A  C +  B C  D +  A B  D + A B D =A  C +  B C  D +  A B  D + A B D Fall 2008, Oct 13...ELEC2200-002 Lecture 548 111 11 1 111 A B C D EPI’s in MSOP Selected PIs Pis not selected

49. Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 1049 Comb. Circuit Power Optimization  Given a set of test vectors  Reorder vectors to minimize the number of transitions at primary inputs Combinational circuit (tested by exhaustive vectors) 01010101 00110011 00001111 01111000 Rearranged vector set00110011 produces 7 transitions 00011110 11 transitions

50. Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 1050 Reducing Comb. Test Power 1 1 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 V1V2V3 V4V5 34 1 3 2 2 3 2 1 1 Original tests: V1 V2 V3 V4 V5 10 input transitions Traveling salesperson problem (TSP) finds the shortest distance closed path (or cycle) to visit all nodes exactly once. But, we need an open loop solution. Reordered tests: V1 V3 V5 V4 V2 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 5 input transitions

51. Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 1051 Open-Loop TSP  Add a node V0 at distance 0 from all other nodes.  Solve TSP for the new graph.  Delete V0 from the solution. V1V2V3 V4V5 34 1 3 2 2 3 2 1 1 V0 0 0 0 0 0

52. Combinational Vector Ordering  See: P. Wray, “Minimize test power for benchmark circuit c6288 by optimal ordering of vectors,” ELEC 6270 Class Project Report, Spring 2009, www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/PROJECT/WRAY/ www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/PROJECT/WRAY/  TSP has exponential complexity; good heuristics are available.  For other extensions:  V. Dabholkar, S. Chakravarty, I Pomeranz and S. Reddy, “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application,” IEEE Trans. CAD, vol. 17, no. 12, pp. 1325-1333, Dec. 1998.  Typical average power saving:  30-50%  50-60% with vector repetition (to satisfy peak power)  ? ? ? With inserted vectors (to satisfy peak power) Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 1052

53. Copyright Agrawal, 2007ELEC6270 Spring 09, Lecture 1053 Traveling Salesperson Problem  A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Structures and Algorithms, Reading, Massachusetts: Addison-Wesley, 1983.  E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, 1984.  B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and Experienced Users, Cambridge University Press, 2006.