1. Semiconductor Device Modeling and Characterization – EE5342 Lecture 10– Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/

2. ©rlc L10-16Feb20112 First Assignment e-mail to listserv@listserv.uta.edu –In the body of the message include subscribe EE5342 This will subscribe you to the EE5342 list. Will receive all EE5342 messages If you have any questions, send to ronc@uta.edu, with EE5342 in subject line.

3. ©rlc L10-16Feb20113 Second Assignment Submit a signed copy of the document that is posted at www.uta.edu/ee/COE%20Ethics%20Statement%20Fall%2007.pdf

4. ©rlc L10-16Feb20114 Additional University Closure Means More Schedule Changes Plan to meet until noon some days in the next few weeks. This way we will make up for the lost time. The first extended class will be Monday, 2/14. The MT changed to Friday 2/18 The P1 test changed to Friday 3/11. The P2 test is still Wednesday 4/13 The Final is still Wednesday 5/11.

5. MT and P1 Assignment on Friday, 2/18/11 Quizzes and tests are open book –must have a legally obtained copy-no Xerox copies. –OR one handwritten page of notes. –Calculator allowed. A cover sheet will be published by Wednesday, 2/16/11. ©rlc L10-16Feb20115

6. 6 Ideal Junction Theory Assumptions E x = 0 in the chg neutral reg. (CNR) MB statistics are applicable Neglect gen/rec in depl reg (DR) Low level injections apply so that  n p < p po for -x pc < x < -x p, and  p n < n no for x n < x < x nc Steady State conditions

7. ©rlc L10-16Feb20117 Forward Bias Energy Bands EvEv EcEc E Fi xnxn x nc -x pc -x p 0 q(V bi -V a ) E FP E FN qV a x Imref, E Fn Imref, E Fp

8. ©rlc L10-16Feb20118 Law of the junction (follow the min. carr.)

9. ©rlc L10-16Feb20119 Law of the junction (cont.)

10. ©rlc L10-16Feb201110 Law of the junction (cont.)

11. ©rlc L10-16Feb201111 Injection Conditions

12. ©rlc L10-16Feb201112 Ideal Junction Theory (cont.) Apply the Continuity Eqn in CNR

13. ©rlc L10-16Feb201113 Ideal Junction Theory (cont.)

14. ©rlc L10-16Feb201114 Ideal Junction Theory (cont.)

15. ©rlc L10-16Feb201115 Excess minority carrier distr fctn

16. ©rlc L10-16Feb201116 Carrier Injection -x p xnxn -x pc 0 ln(carrier conc) ln N a ln N d ln n i ln n i 2 /N d ln n i 2 /N a x nc x ~V a /V t

17. ©rlc L10-16Feb201117 Minority carrier currents

18. ©rlc L10-16Feb201118 Evaluating the diode current

19. ©rlc L10-16Feb201119 Special cases for the diode current

20. ©rlc L10-16Feb201120 Ideal diode equation Assumptions: –low-level injection –Maxwell Boltzman statistics –Depletion approximation –Neglect gen/rec effects in DR –Steady-state solution only Current dens, J x = J s expd(V a /V t ) –where expd(x) = [exp(x) -1]

21. ©rlc L10-16Feb201121 Ideal diode equation (cont.) J s = J s,p + J s,n = hole curr + ele curr J s,p = qn i 2 D p coth(W n /L p )/(N d L p ) = qn i 2 D p /(N d W n ), W n > L p, “long” J s,n = qn i 2 D n coth(W p /L n )/(N a L n ) = qn i 2 D n /(N a W p ), W p > L n, “long” J s,n > N d

22. ©rlc L10-16Feb201122 Diffnt’l, one-sided diode conductance VaVa IDID Static (steady- state) diode I-V characteristic VQVQ IQIQ

23. ©rlc L10-16Feb201123 Diffnt’l, one-sided diode cond. (cont.)

24. ©rlc L10-16Feb201124 Charge distr in a (1- sided) short diode Assume N d << N a The sinh (see L12) excess minority carrier distribution becomes linear for W n << L p  p n (x n )=p n0 expd(V a /V t ) Total chg = Q’ p = Q’ p = q  p n (x n )W n /2 xnxn x x nc  p n (x n ) W n = x nc - x n Q’ p pnpn

25. ©rlc L10-16Feb201125 Charge distr in a 1- sided short diode Assume Quasi-static charge distributions Q’ p = Q’ p = q  p n (x n )W n /2 d  p n (x n ) = (W/2)* {  p n (x n,V a +  V) -  p n (x n,V a )} xnxn x x nc  p n (x n,V a ) Q’ p pnpn  p n (x n,V a +  V)  Q’ p

26. ©rlc L10-16Feb201126 Cap. of a (1-sided) short diode (cont.)

27. ©rlc L10-16Feb201127 General time- constant

28. ©rlc L10-16Feb201128 General time- constant (cont.)

29. ©rlc L10-16Feb201129 General time- constant (cont.)

30. ©rlc L10-16Feb201130 References *Fundamentals of Semiconductor Theory and Device Physics, by Shyh Wang, Prentice Hall, 1989. **Semiconductor Physics & Devices, by Donald A. Neamen, 2nd ed., Irwin, Chicago. M&K = Device Electronics for Integrated Circuits, 3rd ed., by Richard S. Muller, Theodore I. Kamins, and Mansun Chan, John Wiley and Sons, New York, 2003. 1 Device Electronics for Integrated Circuits, 2 ed., by Muller and Kamins, Wiley, New York, 1986. 2 Physics of Semiconductor Devices, by S. M. Sze, Wiley, New York, 1981. 3 Physics of Semiconductor Devices, Shur, Prentice- Hall, 1990.