1. “Lab. 5” – Updating Lab. 3 to use DMA Test we understand DMA by using some simple memory to memory DMA Make life more interesting, since hardware is involved, by using DMA to send out SPI signals

2. 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 2 / 30 Transfer array using “normal array handling” Normal code P0  address of start_array[0]; P1  address of final_array[0]; SPI -- point to SPI_TDBR R0  max-value needed to transfer When SPI ready -- do transfer R1  How many values already transferred Even more processor waiting R1 = 0; LOOP: CC = R0 <= R1 IF CC JUMP DONE: R2 = [P0++]; VERY BIG PIPELINE [P1++] = R2; LATENCY ISSUES JUMP LOOP; MANY INTERNAL PROCESSOR STALLS DONE: WHILE WAIT FOR R2 TO BE Do something else READ, STORED and then TRANSMITTED

3. 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 3 / 30 Concept of a basis MEMDMA and SPI DMA task DMA DMA_source_address_register  address of start_array[0]; DMA_destination_address_register  address of final_array[0]; DMA_max_count_register  max-value needed to transfer DMA_count_register  How many values already transferred R1 = 0; SPI destination is SPI_TDBR LOOP: DMA hardware must “know” how to wait CC = R0 <= R1 until SPI hardware is ready IF CC JUMP DONE: R2 = [P0++]; DMA_enable = true [P1++] = R2; Miminized pipeline issues JUMP LOOP; DONE: Do something else Processor can do something else while DMA is working

4. Chapter 9 of the Blackfin Hardware book 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 4 / 30

5. Design expected functionality of simple MEMDMA task #define NUMPTS 1024 section (“SDRAM”) int destArray[NUMPTS]; int sourceArray[NUMPTS]; TEST(simpleDMAtask) { Set_ArrayZero(destArray); Set_KnownValues(sourceArray); DoMEMDMATransfer(sourceArray, destArray, NUMPTS ); CHECK_ARRAY_EQUAL(sourceArray, destArray, NUMPTS ): …. Other tests here …. } 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 5 / 30

6. DMA registers we need to worry about 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 6 / 30 Final exam question ideas Other test examples Did the hardware think it transferred all the required values? CHECK(NUMPTS, *pMDMA_S0_CURR_X_COUNT); CHECK(NUMPTS, *pMDMA_D0_CURR_X_COUNT);

7. Actual code 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 7 / 30 Not good as final code in a program as involves a wait

8. 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 8 / 30 Source DMA – read Destination DMA – write

9. 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 9 / 30 DMA register detail -- status RO W1C bits Why only Destination DMA status considered?

10. 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 10 / 30

11. Final test result 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 11 / 30 Placing array in external memory

12. Why the failures? 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 12 / 30 X_COUNT = 0. Perhaps this register only useful when doing DMA (how much done before error occurred) – not useful when done What one line did I change to fix code?

13. Try the same with SPI DMA 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 13 / 30 Essentially identical code to InitSPI( ) before (Lab3)

14. Design the tests to check if working 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 14 / 30

15. Concept correct – implementation wrong 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 15 / 30 The book says there is only one channel for non-memory DMA

16. Would this work We can change *pMDMA_S0_START_ADDR to *pDMA0_START_ADDR perhaps but how handle the SPI destination? 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 16 / 30

17. Use some ideas from Lab. 2 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 17 / 30 Specific DMA channel for SPI? This tells us Channel 5 dedicated to SPI register_handler(ik_ivg10,…. IMASK |= 0x00001000 Something new if we “make mistakes”

18. First attempt at the code 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 18 / 30 Just guessed at the DMA register names based on earlier code Need to check the bit positions

19. 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 19 / 30 Need to check the bit usage on CONFIG and STATUS registers

20. Second attempt at the code 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 20 / 30 Final exam hint Common error in the lab. Why did it happen? How do you fix?

21. Code “hangs” – where you might expect it to hang Final exam debug question – How would you determine if the code got into ISR and perhaps is now hanging there? Answer never got to the ISR – if “infinite loop” in ISR then would not be showing the “infinite loop” here 3/13/2016DMA (repeating code), Copyright M. Smith, ECE, University of Calgary, Canada 21 / 30

22. Is the DMA channel running at all? Set break point to check 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 22 / 30 IMASK set Transferred 1 SPI_TDBR = 0

23. Based on debug information IMASK is set correctly We transferred 1 “something” Is direction correct? Final Exam hint on testing sourceArray[0] is being set to 0 as first thing to transfer to SPI SPI_TDBR has reset value is 0 Which of the two zeros are we seeing? Need better array values to use during testing 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 23 / 30

24. Run again after fixing test *pSPI_TDBR = 0x100 This is not the reset value (0) so correct DMA transfer did occur From Lab. 2 – is SIC_IMASK correct? 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 24 / 30 I also see that the DMA interrupts are not set Previous Memory DMA code set interrupt on MDMA_D0 channel – which we now don’t use.

25. Set DMA Interrupt bit Check SIC_IMASK Setting 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 25 / 30

26. Check SIC_IMASK setting *pSIC_IMASK |= 0x00001000 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 26 / 30

27. With SIC_IMASK fixed We go immediately into ISR Still to know When did interrupt occur (at what line of code)? Does interrupt clear? Set break point at StartSPIDMA( ) and then step through code to find out (F11) 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 27 / 30

28. Single step results Problem occurs “before we start DMA” And we never get out of ISR 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 28 / 30

29. Trying starting SPI after DMA 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 29 / 30

30. First transfer is correct None of the others Only ever transfers the “first” element of sourceArray 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 30 / 30 Hangs here when doing line 92Since hanges second time around loop

31. Since hangs inside SetupSPIDMA “2 nd ” time around 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 31 / 30

32. Test to transfer many First test works Second test -- Hangs again Try stopping and restarting SPI and DMA 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 32 / 30 Final exam hint Nasty Code defect here

33. Why does the first test fail and the second test pass? 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 33 / 30

34. Final exam answer would need understanding of what a FIFO is. 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 34 / 30

35. Test Driven Development Next stage We wrote the tests Wrote code to satisfy the tests Modified the tests “Code” just runs Sometimes test fails first time but passes second time – indication of a “race” condition (SPI_BAUD transfer rate slower than Blackfin?) We now need to keep the tests and REFACTOR the code to make more use-able With TTCOS (Lab. 3) need to make run without interrupts. 3/13/2016DMA, Copyright M. Smith, ECE, University of Calgary, Canada 35 / 30