1. AIDA design review Davide Braga Steve Thomas ASIC Design Group 09 October 2008

2. 31 July 2008AIDA design review2 X10 stage - comparator Comparator threshold adjustment to reduce offset Clamping of the x10 gain stage performed by latched comparator to avoid saturation and hence big current spikes

3. 31 July 2008AIDA design review3 Offset (Monte Carlo results) Offset preamp:σ~0.5mV(AC coupled to shaper, does not propagate to comparator) Offset shaper:σ~2mV Offset x10 stage:σ~3mV Offset comparator:σ~30mV!(~ 10 times offset previous stage!)

4. 31 July 2008AIDA design review4 Comparator Threshold The threshold is added to the mean value of the x10 stage output voltage. It is generated by a selectable current (8bit) flowing in a resistor The RC filter has a distributed reset for recovery

5. 31 July 2008AIDA design review5 Comparator Threshold Selectable threshold: Minimum value: V th_ min ~=7mV ~=9800eV (Noise after x10gain stage expected to be σ n ~=3.5mV → 5σ n =17.5mV)

6. 31 July 2008AIDA design review6 Comparator Hysteresis Built-in feature (not selectable) to avoid noise on comparator output: comparator fires at: V in >V th +V hyst. V in <V th -V hyst. V hyst now set to ~10mV

7. 31 July 2008AIDA design review7 X10 gain stage clamp Most signal would saturate the x10 stage output, causing big (and long!) variations in current This can be avoided clamping the amplifier to a unity-gain configuration after the comparator has fired

8. 31 July 2008AIDA design review8 X10 gain stage clamp - latch The comparator responsible for the clamping must be latched not to let the amplifier come back to the x10 gain configuration A timed signal will reset the latch once the signal has disappeared

9. 31 July 2008AIDA design review9 Current stabilization Another measure has been taken to reduce current oscillation in the comparator by inserting a dummy branch which counterbalances the drop in current consumption in the device

10. 31 July 2008AIDA design review10 Transient: false firing When the reset comes off it causes “small” activity in the shaper, which is enough to fire the comparator and also to be store on the peak hold. The comparator must be masked and the peak hold could be set in hold mode to decouple it from the shaper output Shaper Peak Hold Resert shaper Out comparator

11. 31 July 2008AIDA design review11 Layout “left to right” channel layout, with LEC/MEC and HEC in parallel Grid distribution of power supply (“Horizontal” and “vertical”) to minimize impedence and voltage fluctuation across the chip

12. 31 July 2008AIDA design review12 ~7mm ~2mm Bond-wire parasitics: C=  L/cosh -1 (a/d) a=~7mm,d~25  m, L~1mm which gives C~4fF Injected charge Q=CV~12fC=75ke for single wire “Dummy” wires have opposite polarity signals. Electric field drops as r 2 for a dipole, giving much lower coupling capacitance ~2mm

13. 31 July 2008AIDA design review13 PADs (detail)