1. Design AXI Master

2. Agenda Understanding Zynq AXI Master IP axi_user_npi
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3. What is AXI? AXI is Part of AMBA: Advanced Microcontroller
Variations of AXI
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4. Variations of AXI AXI4 AXI4-Lite: AXI4-Stream: Memory mapped
Register mapped
AXI4-Stream:
Streaming
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5. Too COMPLEX…. Why Xilinx Choose AXI? 1 2 3 4 6 5 7 8 BRAM Microblaze
MPMC
LMB 2
External
Memory
Xilinx Cache Link
Too COMPLEX…. 3
VFBC
Video 4
TEMAC
Local Link 6
Hardware
Accelerator 5
FSL
NPI
Custom IP
PLBv46 7
GPIO
Timer
SRAM
UART
PLB to IPIF
Bridge 8
Custom IP
IPIF
Page 5
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6. Too Simple …. Why Xilinx Choose AXI? 1 2 2 2 2 2 2 3 BRAM Microblaze
MPMC
LMB 2
External
Memory
AXI
Too Simple …. 2
AXI
Video 2
TEMAC
AXI 2
Hardware
Accelerator 2
AXI
AXI
Custom IP
AXI 2
GPIO
Timer
SRAM
UART
AXI to IPIF
Bridge 3
Custom IP
IPIF
Page 6
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7. AXI Protocol, Channel Channel Read address Write address Read data
Write data
Write response
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8. Best for memory access AXI Protocol, AXI4 Single address multiple data
Burst up to 256 data beats
Data width parameterizable
32, 64, 128, 256
AXI4 READ
AXI4 Write
Best for memory access
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9. Best for register access
AXI Protocol, AXI4_LITE
Single address Single data
No Burst
Data width 32
AXI4-Lite Read
Best for register access
AXI4-Lite Write
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10. AXI Protocol, AXI4_STREAM
No address channel
Not read and write, always just master to slave
Unlimited burst length
Best for video, audio
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11. ZYNQ High Performance Port General Performance Port AXI Master
AXI Slave
Master
Slave
Master
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12. How to Design AXI Master
CIP
Select AXI type
Select Master
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13. How to Design AXI Master, example
MPD
Default parameter
PAO
Order for synthesis
TEST_IP.VHD
Top level
USER_LOGIC.VHD
User logic

14. How to Design AXI Master
User_logic.vhd
Control Burst Transaction

15. Why Design AXI Master To access DDRx Memory Why don’t you use BRAM?
Because BRAM is EASY
But BRAM is TOO SMALL
DDRx is LARGE
But DDRx is not EASY
Zynq Bram 220KB ~ 2180KB
DDRx max 1GB

16. FIFO Instead of IPIC Remove complexity… Remove Complexity
DDRx
IPIC & State Machine
FIFO
User
Logic
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17. Master IP with FIFO, axi_user_npi
IP catalog
Bus
Port
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18. Master IP with FIFO, axi_user_npi
component system is
port (
...
wr_fifo_wr_en : in std_logic;
wr_fifo_clk : in std_logic;
npi_wr_ready : out std_logic;
rd_fifo_rd_en : in std_logic;
npi_rd_ready : out std_logic;
wr_fifo_data : in std_logic_vector(31 downto 0);
rd_fifo_clk : in std_logic;
rd_fifo_full : out std_logic;
rd_fifo_data : out std_logic_vector(31 downto 0);
rd_fifo_empty : out std_logic;
wr_fifo_full : out std_logic;
wr_fifo_empty : out std_logic );
end component;
User logic interface
Simple
It is FIFO
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19. Master IP with FIFO, axi_user_npi
void npi_stop() { }
void npi_start()
void axi_npi_rd(int reg, int src, int cnt_burst, int cnt_repeat)
void axi_npi_wr(int reg, int src, int cnt_burst, int cnt_repeat)
void axi_npi_reset0()
int npi_status(int reg)
How to Run?
Device Driver
Read
Start add
Read Burst Cnt
Repeat Cnt
Write
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20. Simulation Result
Burst Write
Burst Read
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21. Q&A
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