Presentation on theme: "Fast A/D sampler FINAL presentation"— Presentation transcript:
1Fast A/D sampler FINAL presentation Presented By: Tal Goihman, Irit KaufmanInstructor: Mony OrbachWinter 2012
2GoalsProject Goal:Design and implement an A/D system using Xilinx Virtex6 development board for sampling at highest possible rate.Sample to virtex6 development board DDR memory.Transfer the sampled data to PC memory through PCIe and save the data to disk.
3PC H/W Block Diagram ML605 development board FMC125 Fast A/D FMC Conn PCI-E ConnectorFMC ConnVirtex6 FPGAML605 development boardDDR3FMC125 Fast A/DA/D ICPC
6A/D SamplerThe FMC125 is a Quad-Channel ADC that provides four 8-bit ADC channels enabling simultaneous sampling of 1, 2, or 4 5 , 2.5 , 1.25Gsps respectively.Problems:4DSP provides free of charge a reference design only for 1.25Gsps. A reference design for 5Gsps priced at 2300 EU.
8Design Block Diagram “wormhole” AXI4 Implemented In XPS MicroBlazeDDR3Memory Controller (MIG)AXI MasterUARTADC ControlFMC125AggregatorCDMAPCI ExpressAXI SlaveMailboxTimerIn ISE project Navigator“wormhole”AXI4-liteAXI4
9Block Diagram: Main Data Channel FMC125AggregatorAXI MasterDDR3Memory Controller (MIG)AXI SlaveFMC125 delivers data using bit lanes of a proprietary bus running at 125Mhz into the aggregator.Aggregator unites and synchronizes the different channels into a bit bus.AXI Master sends the data over a 256-bit wide AXI bus running at 200Mhz to the AXI Slave interface of the Memory Controller.Memory controller handles Writes to DDR3.FIFO’s and H/W Flow control in every component’s input (and some components output) throughout the channel to achieve highest possible bandwidth.Throughput is measured using a timer from the start of the write operation until assertion of a write done signal from the AXI master16 samples per clock per channelTotal 16*4*125Mhz=8GB/sAggregator synchronizes samples so that all channel’s sample 0 will come togetherAggregator works at 125Mhz, has a 4bit channel enable inputAXI master throughpuf of 256bit/8*200Mhz=6.25GB/s
10AXI Bus backgroundXilinx has adopted AXI bus, which is a standard bus protocol from ARM used in modern ARM SoC.CharacteristicsMemory mapped, 32-bit addressesWrite Address, write data, write response, read address, read dataVariable width, clock & burst length over a single bus.
12Memory & Memory controller 512MB DDR3 400Mhz (800MT/s)Theoretical bandwidth of MT/s * 64bit / 8 = 6.25GB/sMain channel matched to this theoretical bandwidth (200Mhz * 256bit /8 = 6.25GB/s)Memory & controller isn’t perfect, has a utilization factor.We achieved 5.13GB/s Throughput (82% utilization!)
13Design Block Diagram “wormhole” AXI4 Implemented In XPS MicroBlazeDDR3Memory Controller (MIG)AXI MasterUARTADC ControlFMC125AggregatorCDMAPCI ExpressAXI SlaveMailboxTimerIn ISE project Navigator“wormhole”AXI4-liteAXI4
14Block Diagram: memory to PCIe After the data is sampled to memory the system transfers the first chunk to the Host PC’s DMA buffer.The subsequent chunks are transferred upon receiving a command from the Host PC.Data is read from memory and transferred to PCIe by the DMA engineThroughput was matched to PCIeTransferred in 16MB chunks (the chosen DMA buffer size)Address translation occurs in the PCIe coreTalk about address translation and the issues we had with it
15Block Diagram: PCIe Xilinx Available solutions include: A PCIe integrated block with support for up to x8 gen2. Hard to work with:Need to know inner workings of PCIeNeed to implement several proprietary interfaces with many rules and signalsA wrapper for memory mapped AXI with support for up to x4 gen1 / x2 gen 2Connects to a standard AXI4 busChosen in our design due to high ROIWe chose to use the wrapper due to high ROIx4 gen1 configuration, up to 1GB/sOne 64bit AXI BAR for sample data transfer with Configurable address translation, one PCIe BAR for mailbox communication.
16Block Diagram: MicroBlaze MicroBlaze is a soft-core processor by Xilinx.Runs firmware written in C from a dedicated 64KB BRAM.Firmware communicates with Host PC’s software through a PCIe mailboxSupports a predefined set of commands to accomplish the functional use case and provide debug capabilitiesInitializes and configures the entire system per to the Host PC’s instructions.Provide visual status and information to the user through UART massages.
17Block Diagram: ADC ctrl ADC ctrl is a custom core deigned to enable MicroBlaze to communicate with other custom coresDeveloped using the Create peripharel wizrd in XPS and implements mamory mapped register access through AXI4-liteProvides the following capabilities:Translate the wormhole transactions to / from the FMC125 core.Provide AXI Master with burst count, write start, test signalsProvides the aggregator with enabled ADC channels
18Software Written in C# .NET 4 in VS2012, GUI in WPF Enables simple interaction with the systemUser adjustable burst size,burst count, active channels,output file location andexternal trigger modecompatible with Windows7/8 x64.
19Software: Jungo WinDriver Easy driver creationSimple interface for DMA buffer allocation, read and write operationsSlightly problematic from a .NET environment since it lacks proper documentation, and the wizard generates a non working solutionReference for .NET and DMA was found in a bundled example for PLX chips
20Test EnvironmentVerification of sampled data on DDR3 is accomplished by firmware on MicroBlaze comparing read data with predetermined written patternFMC125 incoming data is observable through ChipScope.Bandwidth was calculated by measuring the time to write a chunk of data using a Timer.Data transfer from memory to PCIe is validated through observing the memory on system and comparing with the data received from PCIe manually.