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Xilinx Confidential Developing Video Applications on Xilinx FPGAs.

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Presentation on theme: "Xilinx Confidential Developing Video Applications on Xilinx FPGAs."— Presentation transcript:

1 Xilinx Confidential Developing Video Applications on Xilinx FPGAs

2 Xilinx / Avnet / Mathworks Video Seminar2 Xilinx Design Flow Video Hardware Development

3 Xilinx / Avnet / Mathworks Video Seminar3 Simulink Executable Spec Purely algorithmic Use abstract blocks Define desired system response

4 Xilinx / Avnet / Mathworks Video Seminar4 Executable Spec Demo

5 Xilinx / Avnet / Mathworks Video Seminar5 Xilinx Design Flow Video Hardware Development

6 Xilinx / Avnet / Mathworks Video Seminar6 Design a Hardware Architecture Floating-point numbers Defining basic elements of Hardware Architecture Compare to Executable Spec

7 Xilinx / Avnet / Mathworks Video Seminar7 Define Fixed-Point Quantization Compare fixed-point error to golden source

8 Xilinx / Avnet / Mathworks Video Seminar8 Redefine Dataflow for Hardware Convert from frames to serial streaming Consistent with CMOS video camera outputs

9 Xilinx / Avnet / Mathworks Video Seminar9 Redefine design using the Xilinx DSP Blockset Xilinx DSP Blockset includes over 100 DSP building blocks that have been optimized for efficient results on Xilinx devices Define partition using GatewayIn / GatewayOut blocks Gateway blocks define the FPGA boundary SysGen token block enables use of netlist generation scripts

10 Xilinx / Avnet / Mathworks Video Seminar10 Model Based Design Demo

11 Xilinx / Avnet / Mathworks Video Seminar11 Xilinx Design Flow Video Hardware Development

12 Xilinx / Avnet / Mathworks Video Seminar12 Video Hardware Verification Flow Reference Model Golden Input Sequences & Test Cases Design Capture Verification Validation 50+ Test Sequences Golden Test Vector Suite Test Cases - Pedestrian Crossing - Abandon Object - Privacy Regions - Object Removal Test Cases - Pedestrian Crossing - Abandon Object - Privacy Regions - Object Removal Golden Test Vectors = ? The Key is Fast Algorithm Confirmation Simulink and the Video and Imaging blockset Early System Architecture Bit True, Not cycle accurate Micro-Architecture IO Definitions Automated TB Generation API Definition Early FPGA Characterization HDL Simulation Back Annotated HDL Sim SysGen CoSim SysGen-VSK HwCoSim SysGen-VSK-VFBC HwCoSim Live Validation, Camera>VSK>Display

13 Xilinx / Avnet / Mathworks Video Seminar13 Accelerating Verification through Hardware Hardware co-verification removes simulation bottleneck – Up to 1000x simulation performance improvement – Automates FPGA and board setup process Design Simulation Time (Seconds) SoftwareHW Co-SimIncrease Beamformer X OFDM BER Test X DUC CFR X Color Space Converter277469x Video Scalar X

14 Xilinx / Avnet / Mathworks Video Seminar14 Eliminating IO Bottlenecks using Hardware Frame Passing System Generator includes specials “Shared Memory Read / Write” blocks to allow large amounts of data to be efficiently passed to hardware from Simulink Boost HW co-sim performance by bundling input data samples together thus reducing simulation to hardware transactions. - Frame size =2880 Boost HW co-sim performance by bundling input data samples together thus reducing simulation to hardware transactions. - Frame size =2880

15 Xilinx / Avnet / Mathworks Video Seminar15 Simulation Runtime Improvements using Hardware Co-simulation Abandon Object Design Sim Time (seconds) Time / frame (seconds) Performance Improvement Original Simulink Abstract Model.5.1N/A With SysGen block*5010baseline SysGen with HW co-sim no frames*165333X slower SysGen with HW co-sim with frames*1533X With input from.mat file*1025X With in/output to.mat file* X * For bit-true hardware accurate simulation models

16 Xilinx / Avnet / Mathworks Video Seminar16 Additional Data from Xilinx Video Development Team Frames 800x x x1080 Non-AcceleratedHW AcceleratedNon AcceleratedHW AcceleratedNon-acceleratedHW Accelerated sec18 sec2238 sec25 sec5310 sec37 sec sec25 sec4728 sec35 secNA62 sec 5NA43 secNA65 secNA128 sec Notes: – 100 Mbps Ethernet link, Effective rate ~5.1 Mbps ML506 Virtex-5 SXT development platform – Payload = 2 * N_Frames * Frame_Size * 32-bits – Load N frames of data, Process N Frames, Store N Frames

17 Xilinx / Avnet / Mathworks Video Seminar17 Hardware Co-Simulation Demo

18 Xilinx / Avnet / Mathworks Video Seminar18 Xilinx Design Flow Video Hardware Development

19 Xilinx / Avnet / Mathworks Video Seminar19 Why Video Systems? Video designs generally include embedded processing for: – Video system control and dataflow control – Table and memory updates – Low performance video processing Xilinx embedded processors allow high-performance video systems on a single chip – Lower cost – Higher performance – Obsolescence proof

20 Xilinx / Avnet / Mathworks Video Seminar20 The VSK Base System Embedded base system provided with the VSK Forms the framework from which video designs are created Includes one MicroBlaze embedded processor Customized using Platform Studio

21 Xilinx / Avnet / Mathworks Video Seminar21 System Generator to Embedded System Generator automatically generates DSP accelerators for use with the Xilinx embedded development environment (XPS) – placed into embedded IP Catalog – Supports PLB or FSL bus – Supports async clocking – Includes driver files and documentation XPS project can be imported into SysGen for system debug

22 Xilinx / Avnet / Mathworks Video Seminar22 Video Starter Kit Reference IP Core Name Use in Reference Designs DVI Pass-throughCamera Frame BufferFrame Buffer DVI_IN and DVI_OUT Yes Camera processing Yes DE_GEN Yes VIDEO_TO_VFBC Yes Video Frame Buffer Controller (VFBC) Yes Provided as a library of “drag and drop” IP for use with the video base system Provides abstraction to the video interface details – Includes SW driver files Platform Studio IP Catalog Generated by SysGen Reference IP included with the VSK

23 Xilinx / Avnet / Mathworks Video Seminar23 Abstracting the Processor Interface “Shared” registers, RAMs and FIFOs are used to create HW / SW abstraction – DSP design connects to a “to” or “from” memory – Memory maps and interface logic is added during RTL generation – Software drivers and documentation are created for easy programming

24 Xilinx / Avnet / Mathworks Video Seminar24 System Design Integration Demo

25 Xilinx / Avnet / Mathworks Video Seminar25 Video Example #1 - VFBC

26 Xilinx / Avnet / Mathworks Video Seminar26 Getting Started with VSK Reference Designs Simplest Frame Buffer Data Transfer DVI Input Frame Buffer DVI Output Basic “real-time” video processing Image Processin g DVI Input DVI Output “Real-time” Frame Buffer Based Video Processing Image Processin g Camera Input Frame Buffer DVI Output

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