1. Developing Video Applications on Xilinx FPGAs
Xilinx Confidential

2. Xilinx Design Flow Video Hardware Development
Xilinx / Avnet / Mathworks Video Seminar

3. Simulink Executable Spec
Purely algorithmic
Use abstract blocks
Define desired system response
Xilinx / Avnet / Mathworks Video Seminar

4. Xilinx / Avnet / Mathworks Video Seminar
Executable Spec Demo
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5. Xilinx Design Flow Video Hardware Development
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6. Design a Hardware Architecture
Floating-point numbers
Defining basic elements of Hardware Architecture
Compare to Executable Spec
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7. Define Fixed-Point Quantization
Compare fixed-point error to golden source
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8. Redefine Dataflow for Hardware
Convert from frames to serial streaming
Consistent with CMOS video camera outputs
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9. Redefine design using the Xilinx DSP Blockset
Gateway blocks define the FPGA boundary
SysGen token block enables use of netlist generation scripts
Xilinx DSP Blockset includes over 100 DSP building blocks that have been optimized for efficient results on Xilinx devices
Define partition using GatewayIn / GatewayOut blocks
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10. Model Based Design Demo
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11. Xilinx Design Flow Video Hardware Development
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12. Video Hardware Verification Flow
Golden Input Sequences & Test Cases
The Key is Fast Algorithm Confirmation
Simulink and the Video and Imaging blockset
Early System Architecture
Bit True, Not cycle accurate
Reference Model
50+ Test Sequences
Micro-Architecture
IO Definitions
Automated TB Generation
API Definition
Early FPGA Characterization
Test Cases
Pedestrian Crossing
Abandon Object
Privacy Regions
Object Removal
Design Capture
Golden Test Vector Suite
Verification
Verification:
Level 1: RTL / HDL using ModelTech (MTI) tools
Level 2: What effects synthesis has in the desing (MTI / XST tool problem?)
Example: reset state in a state machine can be interpreted differently in different tools
Level 3: ModelTech with Sysgen in preparation of doing validation. This is a slow process.
Level 4: once the test hardware is proven from level 3, then we can proceed with hardware-in-the-loop
Level 5: Real time rates
Level 6: Validation beyond golden vectors
HDL Simulation
Back Annotated HDL Sim
SysGen CoSim
Validation
Golden Test Vectors = ?
SysGen-VSK HwCoSim
SysGen-VSK-VFBC HwCoSim
Live Validation, Camera>VSK>Display
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13. Accelerating Verification through Hardware
Hardware co-verification removes simulation bottleneck
Up to 1000x simulation performance improvement
Automates FPGA and board setup process
Design
Simulation Time (Seconds)
Software
HW Co-Sim
Increase
Beamformer
113
2.5
45X
OFDM BER Test
742
.75
989X
DUC CFR
731 23
32X
Color Space Converter
277 4
69x
Video Scalar
10422 92
113X
System Generator supports hardware in the loop flows to over 20 different boards
HIL is supported for both the Simulink and MATLAB modeling environments
JTAG, PCI and Ethernet based HW co-sim is supported
Additional boards can be added to the flow using a wizard in less than 20 minutes
Provides simulation increases up to 1000x
Discovery Questions
Will the FPGA be used for algorithm acceleration or as an FPGA prototype?
Will the FPGA be replaced in the final product?
What benefit will replacing the FPGA bring?
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14. Eliminating IO Bottlenecks using Hardware Frame Passing
System Generator includes specials “Shared Memory Read / Write” blocks to allow large amounts of data to be efficiently passed to hardware from Simulink
Boost HW co-sim performance by bundling input data samples together thus reducing simulation to hardware transactions.
- Frame size =2880
Xilinx / Avnet / Mathworks Video Seminar

15. Simulation Runtime Improvements using Hardware Co-simulation
Abandon Object Design
Sim Time
(seconds)
Time / frame
Performance Improvement
Original Simulink Abstract Model .5 .1
N/A
With SysGen block* 50 10
baseline
SysGen with HW co-sim no frames*
165 33
3X slower
SysGen with HW co-sim with frames* 15 3 3X
With input from .mat file* 2 5X
With in/output to .mat file*
4.2 .8
12X
* For bit-true hardware accurate simulation models
Xilinx / Avnet / Mathworks Video Seminar

16. Additional Data from Xilinx Video Development Team
Frames
800x600
1280x720
1920x1080
Non-Accelerated
HW Accelerated
Non Accelerated
Non-accelerated 1
1243 sec
18 sec
2238 sec
25 sec
5310 sec
37 sec 2
2579 sec
4728 sec
35 sec NA
62 sec 5
43 sec
65 sec
128 sec
Notes:
100 Mbps Ethernet link, Effective rate ~5.1 Mbps
ML506 Virtex-5 SXT development platform
Payload = 2 * N_Frames * Frame_Size * 32-bits
Load N frames of data, Process N Frames, Store N Frames
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17. Hardware Co-Simulation Demo
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18. Xilinx Design Flow Video Hardware Development
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19. Xilinx / Avnet / Mathworks Video Seminar
Why Video Systems?
Video designs generally include embedded processing for:
Video system control and dataflow control
Table and memory updates
Low performance video processing
Xilinx embedded processors allow high-performance video systems on a single chip
Lower cost
Higher performance
Obsolescence proof
Xilinx / Avnet / Mathworks Video Seminar

20. Xilinx / Avnet / Mathworks Video Seminar
The VSK Base System
Embedded base system provided with the VSK
Forms the framework from which video designs are created
Includes one MicroBlaze embedded processor
Customized using Platform Studio
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21. System Generator to Embedded
System Generator automatically generates DSP accelerators for use with the Xilinx embedded development environment (XPS)
placed into embedded IP Catalog
Supports PLB or FSL bus
Supports async clocking
Includes driver files and documentation
XPS project can be imported into SysGen for system debug
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22. Video Starter Kit Reference IP
Core Name
Use in Reference Designs
DVI Pass-through
Camera Frame Buffer
Frame Buffer
DVI_IN and DVI_OUT
Yes
Camera processing
DE_GEN
VIDEO_TO_VFBC
Video Frame Buffer Controller (VFBC)
Provided as a library of “drag and drop” IP for use with the video base system
Provides abstraction to the video interface details
Includes SW driver files
Platform Studio IP Catalog
Reference IP included with the VSK
Generated by SysGen
Xilinx / Avnet / Mathworks Video Seminar

23. Abstracting the Processor Interface
“Shared” registers, RAMs and FIFOs are used to create HW / SW abstraction
DSP design connects to a “to” or “from” memory
Memory maps and interface logic is added during RTL generation
Software drivers and documentation are created for easy programming
Xilinx DSP blocks called “shared memories” are used to create abstraction between the hardware and software.
In Simulink users only connect to the hardware half of the memory
The hardware interface, memory maps and even interrupt logic is added during RTL generation
Software drivers are created with C functions that can be used to access the memory symbolically (by name rather than address location)
Documentation is created automatically to assist in programming
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24. System Design Integration Demo
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25. Xilinx / Avnet / Mathworks Video Seminar
Video Example #1 - VFBC
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26. Getting Started with VSK Reference Designs
Simplest Frame Buffer Data Transfer
DVI
Input
Frame
Buffer
Output
Basic “real-time” video processing
Image
Processing
DVI
Input
Output
“Real-time” Frame Buffer Based Video Processing
Image Processing
Camera
Input
Frame
Buffer
DVI
Output
Xilinx / Avnet / Mathworks Video Seminar