1. Introduction

2. The Tongue-in-Cheek Answer
Why Worry about Power?
The Tongue-in-Cheek Answer
Total Energy of Milky Way Galaxy: 1059 J
Minimum switching energy for digital gate (1 mV): J (limited by thermal noise)
Upper bound on number of digital operations:
Operations/year performed by 1 billion 100 MOPS computers:
Energy consumed in 180 years, assuming a doubling of computational requirements every year (Moore’s Law).

3. Power the Dominant Design Constraint (1)
Cost of large data centers solely determined by power bill …
Google Data Center, The Dalles, Oregon
Columbia River
NY Times, June 06
450,000
400 Millions of Personal Computers worldwide (Year 2000)
- Assumed to consume 0.16 Tera (1012) kWh per year
Equivalent to 26 nuclear power plants
Over 1 Giga kWh per year just for cooling
Including manufacturing electricity
[Ref: Bar-Cohen et al., 2000]
8,000
100,000

4. Power the Dominant Design Constraint
[Ref: R. Schmidt, ACEED’03]

5. Chip Architecture and Power Density
Integration of diverse functionality on SoC causes major variations in activity (and hence power density)
Today: steep gradients
The past: temperature uniformity
Temperature variations cause performance degradation – higher temperature means slower clock speed
[Ref: R. Yung, ESSCIRC’02]

6. Temperature Gradients (and Performance)
Copper hat (heat sink on top not shown)
SiC spreader (chip underneath spreader)
Glass ceramic substrate
IBM Power PC 4 temperature map
Hot spot:
138 W/cm2
(3.6 x chip avg flux)
[Ref: R. Schmidt, ACEED’03]

7. Power the Dominant Design Constraint (2)
© IEEE 2004
Power consumption and Battery Capacity Trends
Mobile Functionality Limited by Energy Budget
Size of mobile sets energy supply
[Ref: Y. Nuevo, ISSCC’04]

8. Mobile Functionality Limited by Energy Budget
© Springer 2005
Energy hierarchy in “ambient intelligent” environment
[Ref: F. Snijders, Ambient Intelligence’05]

9. Battery Storage a Limiting Factor
Basic technology has evolved little
store energy using a chemical reaction
Battery capacity increases between 3% and 7 % per year (doubled during the 90’s, relatively flat before that)
Energy density/size, safe handling are limiting factor
For extensive information on energy density of various materials, check

10. Battery Evolution
Accelerated since the 1990’s, but slower than IC power growth.

11. Battery Technology Saturating
Battery capacity naturally plateaus as systems develop
[Courtesy: M. Doyle, Dupont]

12. Need Higher Energy Density
Fuel cells may increase stored energy more than a order of magnitude
Example: Methanol = 5 kWh/kg
Anode
Electrolyte
Cathode
+ ions
Load
e - + -
Fuel
2H2  4H+ + 4e-
Oxidant
O2 + 4H+ + 4e-  2H2O H O
We saw that the power consumption is gradually increasing. But is there any progress in energy sources? One such effort is found in the development of Direct Methanol Fuel Cell which increases the duration of a battery by an order of magnitude compared with currently widely used Lithium Ion Batteries, giving us a gleam of hope for long-operatable portable systems.
[Ref: R. Nowak, SECA’01]

13. Fuel Cells Methanol fuel-cells for portable pc’s and mp3 players
Portable mp3 fuel cell (300 mW from 10 ml reservoir)
Fuel cell for pc (12 W avg – 24% effiency)
[Ref: Toshiba, ]

14. Micro-batteries When Size is an Issue
Using micro-electronics or thin-film manufacturing techniques to create integrate miniature (back-up) batteries on chip or on board
Battery printed on wireless sensor node
Stencil press for printing patterns
[Courtesy: P. Wright, D. Steingart, UCB]

15. How much Energy Storage in 1 cm3?
J/cm3
mW/cm3/year
Micro Fuel cell
3500
110
Primary battery
2880 90
Secondary battery
1080 34
Ultracapacitor
100
3.2
ultracapacitor
Micro fuel cell
ultracapacitor

16. Power The Dominant Design Constraint (3)
Exciting emerging applications require “zero-power”
Example: Computation/Communication Nodes for Wireless Sensor Networks
Meso-scale low-cost wireless transceivers for
ubiquitous wireless data acquisition that
are fully integrated
Size smaller than 1 cm3
are dirt cheap
At or below 1$
minimize power/energy dissipation
Limiting power dissipation to 100 mW enables energy scavenging
and form self-configuring, robust, ad-hoc networks containing 100’s to 1000’s of nodes
[Ref: J. Rabaey, ISSCC’01]

17. How to Make Electronics Truly Disappear?
From 10’s of cm3 and 10’s to 100’s of mW
To 10’s of mm3 and 10’s of mW

18. Power the Dominant Design Constraint
Exciting emerging applications require “zero-power”
Real-time Health Monitoring
Smart Surfaces
Artificial Skin
Philips Sand module
UCB mm3 radio
UCB PicoCube
Still at least one order of magnitude away

19. How much Energy Can One Scavenge in 1 cm3?
Thermal
Vibrations
mW/cm3
Solar (outside)
15,000
Air flow
380
Human power
330
Vibration
200
Temperature 40
Pressure Var. 17
Solar (inside) 10
Air Flow
Solar

20. A Side Note: What can one do with 1 cm3
A Side Note: What can one do with 1 cm3? Reference case: the human brain
Pavg(brain) = 20 W (20% of the total dissipation, 2% of the weight), Power density: ~15 mW/cm3
Nerve cells only 4% of brain volume
Average neuron density: 70 million/cm3

21. Power versus Energy Power in high performance systems
Heat removal
Peak power - power delivery
Energy in portable systems
Battery life
Energy/power in “zero-power systems”
Energy-scavenging and storage capabilites
Dynamic (energy) vs. static (power) consumption
Determined by operation modes

22. Power Evolution over Technology Generations
Year of Announcement
1950
1960
1970
1980
1990
2000
2010
Module Heat Flux(watts/cm2) 2 4 6 8 10 12 14
Bipolar
CMOS
Vacuum
IBM 360
IBM 370
IBM 3033
IBM ES9000
Fujitsu VP2000
IBM 3090S
NTT
Fujitsu M-780
IBM 3090
CDC Cyber 205
IBM 4381
IBM 3081
Fujitsu M380
IBM RY5
IBM GP
IBM RY6
Apache
Pulsar
Merced
IBM RY7
IBM RY4
Pentium II(DSIP)
T-Rex
Squadrons
Pentium 4
Mckinley
Start of
Water Cooling
Prescott
Jayhawk(dual)
© ASME 2004
Introduction of CMOS over bipolar bought industry 10 years (example: IBM mainframe processors)
[Ref: R. Chu, JEP’04]

23. Power Trends for Processors
1000
© IEEE 2003
x1.4 / 3 years
100
x4 / 3 years 10
Power per chip [W] 1
0.1
MPU
This graph shows the power consumption trend of processors reported in the ISSCC for these 20 years. As you can see, in 1980’s when the supply voltage was kept constant at 5V, the power was increasing 4 times every 3 years. In 1990’s the increase rate was slowed down to 1.4 times every 3 years but the power consumption has been and is steadily increasing and processors consuming more than 100 watt are reported recently.
DSP
0.01
1980
1985
1990
1995
2000
Year
[Ref: T. Sakurai, ISSCC’03]

24. Power Density Trend for Processors
0.1 1 10
100
1000
Design rule [µm]
Scaling variable: k
 k3
10000
 k0.7
MPU
DSP
Scaling the Prime Reason!
© IEEE 2003
P = PDYNAMIC (+ PLEAK)
Constant V scaling and long-channel devices
 PDYNAMIC  k3
Power density : p [W/cm2]
Let’s think about the cause of the power increase. As is well-known, power consists of two parts, that is, dynamic or charging-discharging component and the leakage component. If we re-plot the previous data points with lateral axis being a scaling variable kappa, we can see that in old days when we were using more than a micron as a design rule, the power density increased as cubic of kappa. This is completely explained by the constant voltage scaling scenario where dynamic power increases as kappa cubed. On the other hand, the power increases as kappa to 0.7 in submicron era and this is explained by a normal scaling scenario, where supply voltage is decreased inversely proportional to kappa. So it can be said that the power increase in the past is due to scaling and thus inevitable.
Proportional V scaling and short-channel devices
 PDYNAMIC  k0.7
[Ref: T. Sakurai, ISSCC’03]

25. Evolution of Supply Voltages in the Past5
4.5 4
3.5 3
Supply Voltage (V)
2.5 2
1.5 1
0.5 -1 1 10
Minimum Feature Size (micron)
Supply voltage scaling only from the 1990’s

26. Subthreshold Leakage As an Extra Complication2
0.2
0.4
0.6
0.8 1
1.2
© IEEE 2003 20 40 60 80
100
120
PLEAK
Subthreshold leak
(Active leakage)
Voltage [V]
VDD
Technology node[nm]
Power [µW / gate] 1
Technology node
VTH
PDYNAMIC
Added to the dynamic component, what makes things worse, there is an extra power component, that is, subthreshold leakage component. As technology scales, we have to use lower supply voltage, VDD. Then, we have to decrease the threshold voltage, VTH to maintain appropriate speed. This low VTH in turn increases the subthreshold leakage and in several years, the subthreshold leakage will become a dominant component in power consumption. That is, in the future, the leakage plays an important role not only in stand-by mode but also in an active mode. Here, a gate leakage problem is neglected, which I think device geniuses will solve possibly with high-k gate material. But the subthreshold leakage problem can not be solved by MOSFET structures nor new materials if we rely on the principle of MOSFET anyway.
2002
’04
’06
’08
’10
’12
’14
’16
2002
’04
’06
’08
’10
’12
’14
’16
Year
Year
[Ref: T. Sakurai, ISSCC’03]

27. Static Power (Leakage) may Ruin Moore’s Law
1/100
10000
Leakage
© IEEE 2003
1000
Dynamic
x1.4 / 3 years
x1.1 / 3 years
100
ITRS requirement
x4 / 3 years 10
Power per chip [W] 1
If we add a future perspective to the power trend, the figure becomes like this. The ITRS roadmap requests that the power increase should be almost zero in this decade, while dynamic power alone increases 1.4 times per 3 years and if we add the leakage component, the increase becomes the red dash-dot line. Thus the power increase can be a big stumbling block to the Moore’s law. Two orders of magnitude reduction of power is necessary in ten years from now to meet the requirement.
0.1
MPU
Processors published in ISSCC
DSP
0.01
1980
1985
1990
1995
2000
2005
2010
2015
Year
[Ref: T. Sakurai, ISSCC 03]

28. Power Density Increases
Unsustainable in the long term
10000
Sun’s Surface
Rocket Nozzle
1000
Nuclear Reactor
Power Density (W/cm2)
100
Upper Bound?
8086 10
Hot Plate P6
8008
Pentium® proc
8085
386
4004
286
486
8080 1
1970
1980
1990
2000
2010
Year
[Courtesy: S. Borkar, Intel]

29. Projecting Into the Future
FD-SOI
Dual Gate
Compute density: k3
Leakage power density: k2.7
Active power density: k1.9
Power density (active and static) accelerating anew.
Technology innovations help, but impact limited.
2005 ITRS – Low operating power scenario
2003 ITRS – Low operating power scenario

30. Complicating the Issue: The Diversity of SoCs
Let’s take another look at the system level. These four pi charts show power distributions in different chips. As you can see, power distribution is very diverse. Before starting the power-aware design, we have to check what portion of the target system consumes power. Some chips consume lots of power at I/O’s as is the case in the lower right chart.
Power budgets of leading general purpose (MPU) and special purpose (ASSP) processors
[Ref: many combined sources]

31. Supply and Threshold Voltage Trends
Slide 1.30 1
0.9
0.8
0.7
VDD/VTH = 2!
VDD
0.6
0.5
0.4
0.3 VT
0.2
0.1
2004
2006
2008
2010
2012
2014
2016
2018
2020
2022
Voltage reduction projected to saturate
Optimistic scenario – some claims exist that VDD may get stuck around 1V
[Ref: ITRS 05, Low power scenario]

32. A 20 nm Scenario Assume VDD = 1.2V FO4 delay < 5 ps
Assuming no architectural changes, digital circuits could be run at 30 GHz
Leading to power density of 20 kW/cm2 (??)
Reduce VDD to 0.6V
FO4 delay ≈ 10 ps
The clock frequency is lowered to 10 GHz
Power density reduces to 5 kW/cm2 (still way too high)
[Ref: S. Borkar, Intel]

33. A 20 nm Scenario (cntd)
Assume optimistically that we can design FETs (Dual-Gate, FinFet, or whatever) that operate at 1 kW/cm2 for FO4 = 10 ps and VDD = 0.6 V [Frank, Proc. IEEE, 3/01]
For a 2cm x 2cm high-performance microprocessor die, this means 4kW power dissipation.
If die power has to be limited to 200W, only 5% of these devices can switching at any time, assuming that nothing else dissipates power.
[Ref: S. Borkar, Intel]

34. An Era of Power-Limited Technology Scaling
Technology innovations offer some relief
Devices that perform better at low voltage without leaking too much
But also are adding major grieve
Impact of increasing process variations and various failure mechanisms more pronounced in low-power design regime.
Most plausible scenario
Circuit and system level solutions essential to keep power/energy dissipation in check
Slow down growth in computational density, and use obtained slack to control power density increase.
Introduce design techniques to operate circuit at nominal, not worst-case, conditions

35. Some Useful References …
Selected Keynote Presentations
Fred Boekhorst, ”Ambient intelligence, the next paradigm for consumer electronics: How will it affect Silicon?, ”  Digest of Technical Papers ISSCC,  pp. 28-31, Febr. 02.
Theo A. C. M. Claasen, “High speed: Not the only way to exploit the intrinsic computational power of silicon,” Digest of Technical Papers ISSCC,  pp. 22-25, Febr. 99.
Hugo De Man, “Ambient intelligence: Gigascale dreams and nanoscale realities,”  Digest of Technical Papers ISSCC, pp. 29-35, Febr. 05.
Patrick P. Gelsinger, Microprocessors for the new millennium: Challenges, opportunities, and new frontiers,”  Digest of Technical Papers ISSCC,  pp. 22-25, Febr. 01.
Gordon E. Moore, “No exponential is forever: But "Forever" can be delayed!,”  Digest of Technical Papers ISSCC,  pp. 20-23, Febr. 03.
Yrjö Neuvo, ”Cellular phones as embedded systems,”  Digest of Technical Papers ISSCC, pp. 32-37, Febr. 04.
Takayasu Sakurai, ”Perspectives on power-aware electronics,”  Digest of Technical Papers ISSCC, pp. 26-29, Febr. 03.
Robert Yung, Stefan Rusu, and Ken Shoemaker, Future trend of microprocessor design,  Proceedings ESSCIRC, Sept
Books and Book Chapters
S. Roundy, P. Wright and J.M. Rabaey, "Energy Scavenging for Wireless Sensor Networks," Kluwer Academic Publishers, 2003.
F. Snijders, “Ambient Intelligence Technology: An Overview,” In Ambient Intelligence, Ed. W. Weber et al, pp , Springer, 2005.
T. Starner and J. Paradiso, “Human-Generated Power for Mobile Electronics,” in “Low-Power Electronics”, C. Piguet, Editor, pp , CRC Press 05.

36. Some Useful References (cntd)
Publications
A. Bar-Cohen, S. Prstic, K. Yazawa, M. Iyengar. “Design and Optimization of Forced Convection Heat Sinks for Sustainable Development”, Euro Conference –New and Renewable Technologies for Sustainable, 2000.
S. Borkar, numerous presentations over the past decade …
R. Chu, “The Challenges of Electronic Cooling: Past, Current and Future,” Journal of Electronic Packaging, Vol 126, pp. 491, Dec
D. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proceedings of the IEEE, Volume 89,  Issue 3,  pp. 259 – 288 , March 2001.
International Technology Roadmap for Semiconductors,
J. Markoff and S. Hansell, “Hiding in Plain Sight, Google Seeks More Power”, NY Times, June 2006.
R. Nowak, “A DARPA Perspective on Small Fuel Cells for the Military,” presented at Solid State Energy Conversion Alliance (SECA) Workshop, Arlington, March 2001.
J. Rabaey et al. "PicoRadios for wireless sensor networks: the next challenge in ultra-low power design,” Proc IEEE ISSCC Conference, pp.200-1, San Francisco, February 2002.
R. Schmidt, “Power Trends in the Electronics Industry – Thermal Impacts,” ACEED03, IBM Austin Conference on Energy-Efficient Design, 2003.
Toshiba, “Toshiba Announces World's Smallest Direct Methanol Fuel Cell With Energy Output of 100 Milliwatts,” June 2004.