1. Copyright © 2003 Texas Instruments. All rights reserved.
DSP C5000
Chapter 9
Understanding and Programming the Multi-channel Buffered Serial Port (McBSP)
Copyright © 2003 Texas Instruments. All rights reserved.

2. Differences between C5416 and C5510 Configuration with CSL
Outline
Application of McBSP
McBSP on
C5416 and C5510
Differences between C5416 and C5510
Configuration with CSL
References

3. Application of McBSP McBSP = Multichannel Buffered Serial Port
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D - D/A and serial devices.
Direct connection to other C5000 devices,
Usually works in connection with DMA
Depending on the specific device, the ‘C54x digital signal processor provides
multiple high-speed, full-duplex, multichannel buffered serial ports (McBSPs)
that allow direct interface to other ’C54x devices, codecs and other devices in
a system. The ’C5402 provides two, the ’C5410 three, and the ’C5420 six McBSPs.
They are based on the standard serial port interface found on other ’C54x devices.

4. Audio System using DMA and McBSP
Here the codec means Coder Decoder.
Let’s take a closer look at how the buffers are organized...

5. What about the output buffers?
Ping-Pong Buffers
In order to make the application less real-time critical, the input is double buffered
These buffers are called ping-pong buffers
The configuration is that of a two frame circular buffer
First fill one buffer, then fill the other, then switch back to the first
What about the output buffers?

6. What needs to happen to the DMA Channels?
The Flow 1 of 4
What needs to happen to the DMA Channels?

7. What buffers can the application use to process?
The Flow 2 of 4
What buffers can the application use to process?

8. How do we know when new buffers are ready?
The Flow 3 of 4
How do we know when new buffers are ready?

9. And everything starts over…on to the hardware!!
The Flow 4 of 4
And everything starts over…on to the hardware!!

10. McBSP on C5416 and C5510 C5416 and C5510 McBSP are very similar
The small differences will be discussed in a later section
3 McBSPs on C5416 and C5510
Basic pins on serial ports (R for Read and X for Transmit):
BDR or BDX: serial data
BCLKR or BCLKX: clock at bit rate
BFSR or BFSX: frame synchronization (word rate)

11. Multi-Channel Buffered Serial Port (McBSP)
The McBSP consists of a data path and a control path connected to external
devices by seven pins.
There are actually two DRR and 2 DXR registers (DRR1, DRR2, DXR1, DXR2), each 16-bits wide.
But only ONE register is shown here that can accommodate data from 8 to 32 bits.
DRR2, RBR2, RSR2, DXR2, and XSR2 registers are not utilized (written, read,
or shifted) if the receive/transmit word length, R/XWDLEN[1,2], is specified for
8-, 12-, or 16-bit mode.
Data are communicated to devices interfacing the McBSP via the data transmit
(DX) pin for transmit and the data receive (DR) pin for receive. Control information
in the form of clocking and frame synchronization is communicated via
CLKX, CLKR, FSX, and FSR. The ’C54x communicates with the McBSP through
16-bit-wide control registers accessible via the internal peripheral bus.
The CPU or the DMA controller reads the received data from the data receive
register (DRR[1,2]) and writes the data to be transmitted to the data transmit
register (DXR[1,2]). Data written to DXR[1,2] is shifted out to DX via the transmit
shift register (XSR[1,2]). Similarly, receive data on the DR pin is shifted into
the receive shift register (RSR[1,2]) and copied into the receive buffer register
(RBR[1,2]). RBR[1,2] is then copied to DRR[1,2], which can be read by the CPU
or the DMA controller. This allows simultaneous movement of internal and external
data communications.
Full duplex, max bit rate = ½ CPU clock
Word length: 8, 12, 16,20, 24, 32
Frame length (between FS): words

12. McBSP Interface Signals
The receive operation is triple buffered and the transmit operation is double buffered.
Receive data arrive on DR and are shifted into RSR[1,2]. Once a full word (8-,
12-, 16-, 20-, 24-, or 32-bit) is received, RSR[1,2] is copied to the receive buffer
register, RBR[1,2], only if RBR[1,2] is not full. RBR[1,2] is then copied to
DRR[1,2], unless DRR[1,2] is not read by the CPU or DMA.
Transmit data is written by the CPU or DMA to DXR[1,2]. If there is no data in
XSR[1,2], the value in DXR[1,2] is copied to XSR[1,2]; otherwise, DXR[1,2] is
copied to XSR[1,2] when the last bit of data is shifted out from DX. After transmit
frame synchronization, XSR[1,2] begins shifting out the transmit data from DX.

13. More Features of the McBSP 1 of 2
Double-buffered transmission and triple-buffered reception
Independent clocking and framing for transmit and receive.
Capability to send interrupts to the CPU and DMA event to the DMA controller.
External shift clock generation or an internal programmable-frequency clock
Highly programmable internal clock and frame generation
Programmable sample rate generator
128 channels.
In addition, the McBSP has the following capabilities:
Direct interface to:
T1/E1 framers
MVIP switching compatible and ST-BUS compliant devices including:
MVIP framers
H.100 framers
SCSA framers
IOM-2 compliant devices
AC97 compliant devices (the necessary multi-phase frame-synchronization capability is provided.)
IIS compliant devices
SPI devices

14. More Features of the McBSP 2 of 2
Programmable polarity for both frame synchronization and data clocks
8-bit data transfers with option of LSB or MSB first
-Law and A-Law companding
Companding (COMpress and exPAND) hardware allows compression and expansion
of data in either -law or A-law format. The companding standard
employed in the United States and Japan is  -law. The European companding
standard is referred to as A-law. The specification for -law and A-law log PCM
is part of the CCITT G.711 recommendation.
A-law and  -law allows 13 bits and 14 bits of dynamic range, respectively. Any values outside this range will
be set to the most positive or most negative value. Thus, for companding to
work best, the data transferred to and from the McBSP via the CPU or DMA
must be at least 16-bit wide data.
The  -law and A-law formats encode data into 8-bit code words. Companded
data is always 8-bits wide; therefore, the appropriate (R/X)WDLEN[1,2] must
be set to 0, indicating 8-bit wide serial data stream. If companding is enabled
and either phase of the frame does not have 8-bit word length, then companding
continues as if the word length is eight bits.
When companding is used, transmit data is encoded according to specified
companding law, and receive data is decoded to 2’s complement format. Companding
is enabled and the desired format selected by appropriately setting
(R/X)COMPAND in (R/X)CR2.
Compression occurs during the process of copying data from DXR1-to-XSR1
and from RBR1-to-DRR1,
For transmit data to be compressed properly, the data should be left-justified
when it is written to DXR1. When using m-law, the 14 data bits are left-justified
in the register, with the remaining two low-order bits filled with zeros.
Companding internal data
If the McBSP is otherwise unused (serial port X/R sections are reset), the companding
hardware can compand internal data. This can be used to:
Convert linear to the appropriate m-law or A-law format.
Convert m-law or A-law to the linear format.
Observe the quantization effects in companding by transmitting linear
data, and compressing and re-expanding this data. This is only useful if
both XCOMPAND and RCOMPAND enable the same companding format.
There are 2 methods by which the McBSP can compand internal
data. Data paths for these two methods are used to indicate:
1) When both the transmit and receive sections of the serial port are reset,
DRR1 and DXR1 are internally connected through the companding logic.
Values from DXR1 are compressed, as selected by XCOMPAND, and
then expanded, as selected by RCOMPAND. Note that RRDY and XRDY
bits are not set. However, data is available in DRR1 within four CPU clocks
after being written to DXR1. The advantage of this method is its speed.
The disadvantage is that there is no synchronization available to the CPU
and DMA to control the flow. Note that DRR1 and DXR1 are internally connected
if the (X/R)COMPAND bits are set to 1xb, i.e., compand using Alaw
or m-law.
2) The McBSP is enabled in digital loop back mode with companding appropriately
enabled by RCOMPAND and XCOMPAND. Receive and transmit
interrupts (RINT when RINTM = 0 and XINT when XINTM = 0) or synchronization
events (REVT and XEVT) allow synchronization of the CPU or
DMA to these conversions, respectively. Here, the time for this companding
depends on the serial bit rate selected.

15. Bit Ordering
Normally, transfers using the McBSP are sent and received with the MSB first.
Certain 8-bit data protocols (that do not use companded data) require the LSB to be transferred first:
By setting (R/X)COMPAND = 01b in (R/X)CR2, the bit ordering of 8-bit words is reversed (LSB first) .
This feature is only enabled if the appropriate (R/X)WDLEN[1,2] is set to 0, (8-bit words).
If either phase of the frame does not have an 8-bit word length, the McBSP assumes the word length is 8 bits, and LSB-first ordering is done.

16. McBSP Data and Control Paths
The letter B before the pin names is omitted on this figure, ie DX instead of BDX.
It will also be the case in the following slides.
Apart from the data registers DRR1, DRR2, DXR1, DXR2,
XSR[1,2]). RSR[1,2] and RBR[1,2]), the McBSP includes control registers.
These registers are accessible to the CPU to configure the control mechanism
of the McBSP.
The control block consists of internal clock generation, frame-synchronization
signal generation, and their control and multichannel selection.
This control block sends notification of important events to the CPU and DMA
controller via the two interrupt and four event signals.

17. McBSP Control Registers for Clock and Frame Synchronisation and Control
The x at the end of a register name represents the number of the McBSP device: McBSP 0,1 or 2.

18. McBSP Control Registers for Channel Selection
8 partitions A, B, C, D, E, F, G, H
Earlier versions of ‘C54 such as ‘C5410 or ‘C5420 only contained partitions A and B.
The x at the end of a register name represents the number of the McBSP device: McBSP 0,1 or 2.

19. McBSP Configuration Via SPCR1, SPCR2 and PCR registers
These contain status information and bits that can be configured for the required operation.
PCR
Configures the McBSP pins as inputs or outputs during normal serial port operation,
Configures the pins as general purpose inputs or outputs during receiver and/or transmitter reset.

20. Configuration of McBSP, SPCR1 Register
DLB= Digital Loop Back Mode
RJUST = Receive Sign-Extension and Justification Mode
CLKSTP = Clock Stop Mode
DXENA = DX delay Enabler
ABIS = A-bis mode
RINTM = Receive Interrupt Mode
RSYNCERR = Receive Synchronization Error
RFULL = Receiver shift Register full
RRDY = Receiver Ready
RRST = Receiver Reset
DLP = Digital Loop Back Mode
DLB = 0 Digital loop back mode disabled
DLB = 1 Digital loop back mode enabled
RJUST Receive Sign-Extension and Justification Mode
RJUST = 00 Right-justify and zero-fill MSBs in DRR[1,2]
RJUST = 01 Right-justify and sign-extend MSBs in DRR[1,2]
RJUST = 10 Left-justify and zero-fill LSBs in DRR[1,2]
RJUST = 11 Reserved
RJUST in SPCR1 selects whether data in RBR[1,2] is right or left justified (with
respect to the MSB) in DRR[1,2]. If right-justification is selected, RJUST further
selects whether the data is sign-extended or zero-filled.
CLKSTP Clock Stop Mode
CLKSTP = 0X Clock stop mode disabled. Normal clocking for non-SPI mode.
Various SPI modes when:
CLKSTP = 10 and
CLKXP = 0
Clock starts with rising edge without delay
CLKXP = 1
Clock starts with falling edge without delay
CLKSTP = 11 and
Clock starts with rising edge with delay
Clock starts with falling edge with delay
DXENA DX Enabler.
DXENA = 0 DX enabler is off
DXENA = 1 DX enabler is on
ABIS Mode
ABIS = 0 A-bis mode is disabled
ABIS = 1 A-bis mode is enabled
RINTM Receive Interrupt Mode
RINTM = 00 RINT driven by RRDY (i.e. end of word) and end of
frame in A-bis mode.
RINTM = 01 RINT generated by end-of-block or end-of-frame in
multichannel operation
RINTM = 10 RINT generated by a new frame synchronization
RINTM=11 RINT generated by RSYNCERR
RSYNCERR Receive Synchronization Error
RSYNCERR = 0 No synchronization error
RSYNCERR = 1 Synchronization error detected by McBSP.
RFULL Receive Shift Register (RSR[1,2]) Full
RFULL = 0 RBR[1,2] is not in overrun condition
RFULL = 1 DRR[1,2] is not read, RBR[1,2] is full and RSR[1,2]
is also full with new word
RRDY Receiver Ready
RRDY = 0 Receiver is not ready.
RRDY = 1 Receiver is ready with data to be read from DRR[1,2].
RRST Receiver reset. This resets and enables the receiver.
RRST = 0 The serial port receiver is disabled and in reset state.
RRST = 1 The serial port receiver is enabled.

21. Configuration of McBSP, SPCR2 Register
FREE = Free Running mode (in emulation)
SOFT = Soft bit (in emulation)
FRST = Frame-sync generator Reset
GRST = Sample rate generator Reset
FREE Free Running Mode
FREE = 0 Free running mode is disabled
FREE = 1 Free running mode is enabled
SOFT Soft Bit
SOFT = 0 SOFT mode is disabled
SOFT = 1 SOFT mode is enabled
FRST Frame-Sync Generator Reset
FRST = 0 Frame-synchronization logic is reset. Frame-sync
signal FSG is not generated by the sample-rate generator.
FRST = 1 Frame-sync signal FSG is generated after
(FPER+1) number of CLKG clocks; i.e., all frame
counters are loaded with their programmed values.
GRST Sample-Rate Generator Reset
GRST = 0 Sample rate generator is reset
GRST = 1 Sample rate generator is pulled out of reset. CLKG
is driven as per programmed value in sample rate
generator registers (SRGR[1,2]).

22. Configuration of McBSP PCR Pin Control Register
XIOEN = Transmit general purpose IO mode
RIOEN = Receive general purpose IO mode
FSXM = Transmit Frame-Synchronization Mode
FSRM = Receive Frame-Synchronization Mode
CLKXM, CLKRM = Transmitter (Receiver) clock Mode
CLKS_STAT = Status of CLKS pin when GPIO
DX_STAT, DR_STAT = Status of DX (DR) when GPIO
FSXP, FSRP = Transmit (receive) Frame-Sync. Polarity
CLKXP, CLKRP = Transmit (receive) Clock Polarity
XIOEN Transmit general purpose I/O mode only when XRST = 0 in SPCR[1,2]
XIOEN = 0 DX, FSX and CLKX are configured as serial port pins and
do not function as general-purpose I/Os.
XIOEN = 1 DX pin is a general purpose output. FSX and CLKX are
general purpose I/Os. These serial port pins do not
perform serial port operation.
RIOEN Receive general purpose I/O mode only when RRST = 0 in SPCR[1,2]
RIOEN = 0 DR, FSR, CLKR and CLKS are configured as serial port
pins and do not function as general-purpose I/Os.
RIOEN = 1 DR and CLKS pins are general purpose inputs; FSR and
CLKR are general purpose I/Os. These serial port pins do
not perform serial port operation. The CLKS pin is affected
by a combination of RRST and RIOEN signals of the
receiver.
FSXM Transmit Frame-Synchronization Mode
FSXM = 0 Frame-synchronization signal derived from an external source
FSXM = 1 Frame synchronization is determined by the sample rate
generator frame-synchronization mode bit FSGM in SRGR2.
FSRM Receive Frame-Synchronization Mode
FSRM = 0 Frame-synchronization pulses generated by an external
device. FSR is an input pin
FSRM = 1 Frame synchronization generated internally by sample
rate generator. FSR is an output pin except when
GSYNC=1 in SRGR.
CLKXM Transmitter Clock Mode
CLKXM = 0 Transmitter clock is driven by an external clock with CLKX
as an input pin.
CLKXM = 1 CLKX is an output pin and is driven by the internal sample
rate generator.
During SPI mode (when CLKSTP is a non-zero value):
CLKXM = 0 McBSP is a slave and clock (CLKX) is driven by the SPI
master in the system. CLKR is internally driven by CLKX.
CLKXM = 1 McBSP is a master and generates the clock (CLKX) to
drive its receive clock (CLKR) and the shift clock of the
SPI-compliant slaves in the system.
CLKRM Receiver Clock Mode
Case 1: Digital loop back mode not set (DLB = 0) in SPCR1
CLKRM = 0 Receive clock (CLKR) is an input driven by an external clock.
CLKRM = 1 CLKR is an output pin and is driven by the internal sample
Case 2: Digital loop back mode set (DLB=1) in SPCR1
CLKRM = 0 Receive clock (not the CLKR pin) is driven by transmit
clock (CLKX) which is based on the CLKXM bit in the PCR.
CLKR pin is in high-impedance.
CLKRM = 1 CLKR is an output pin and is driven by the transmit clock.
The transmit clock is derived based on the CLKXM bit in the PCR.
CLKS_ STAT CLKS pin status. Reflects value on CLKS pin when selected as a general
purpose input.
DX_STAT DX pin status. Reflects value driven on to DX pin when selected as a general purpose output.
DR_STAT DR pin status. Reflects value on DR pin when selected as a general purpose input.
FSXP Transmit Frame-Synchronization Polarity
FSXP = 0 Frame-synchronization pulse FSX is active high
FSXP = 1 Frame-synchronization pulse FSX is active low
FSRP Receive Frame-Synchronization Polarity FSRP = 0 Frame-synchronization pulse FSR is active high
FSRP = 1 Frame-synchronization pulse FSR is active low
CLKXP Transmit Clock Polarity
CLKXP = 0 Transmit data sampled on rising edge of CLKX
CLKXP = 1 Transmit data sampled on falling edge of CLKX
CLKRP Receive Clock Polarity
CLKRP = 0 Receive data sampled on falling edge of CLKR
CLKRP = 1 Receive data sampled on rising edge of CLKR

23. Receive and Transmit Control Registers RCR and XCR
RFLEN1 = Receive Frame Length 1 (1 to 128 words / frame)
RWDLEN1 = Receive Word Length 1 (8, 12, 16, 20, 24, 32 bits)
RCR2
RPHASE = Receive phases (single or dual frames)
RFLEN2 =Receive Frame Length 2 (1 to 128 words / frame)
RWDLEN2 = Receive Word Length 2 (8, 12, 16, 20, 24, 32 bits)
RCOMPAND = Receive companding mode
RFIG = Receive Frame Ignore
RDATDLY =Receive Data Delay
The receive and transmit control registers (RCR[1,2] and XCR[1,2]) configure
various parameters of the receive and transmit operations, respectively.
RCR1
RFRLEN1 Receive Frame Length
RFRLEN1 = word per frame
RFRLEN1 = words per frame ….
RFRLEN1 = words per frame
RWDLEN1 Receive Word Length
RWDLEN1 = bits
RWDLEN1 = bits
RWDLEN1 = bits
RWDLEN1 = bits
RWDLEN1 = bits
RWDLEN1 = bits
RWDLEN1 = 11X Reserved
RCR2
------
RPHASE Receive Phases
RPHASE = 0 Single-phase frame
RPHASE = 1 Dual-phase frame
RFRLEN2 Receive Frame Length
RFRLEN2 = word per frame
RFRLEN2 = words per frame
RFRLEN2 = words per frame
RWDLEN2 Receive Word Length 2
RWDLEN2 = bits
RWDLEN2 = bits
RWDLEN2 = bits
RWDLEN2 = bits
RWDLEN2 = bits
RWDLEN2 = bits
RWDLEN2 = 11X reserved
RCOMPAND Receive companding mode. Modes other than 00b are only enabled
when the appropriate RWDLEN is 000b, indicating 8-bit data.
RCOMPAND = 00 No companding, data transfer starts with MSB first.
RCOMPAND = 01 No companding, 8-bit data, PHASE: trannsfer starts with LSB first.
RCOMPAND = 10 Compand using m-law for receive data.
RCOMPAND = 11 Compand using A-law for receive data.
RFIG Receive Frame Ignore
RFIG = 0 Receive frame-synchronization pulses after the first restarts the transfer.
RFIG = 1 Receive frame-synchronization pulses after the first are ignored.
RDATDLY Receive data delay
RDATDLY = 00 0-bit data delay
RDATDLY = 01 1-bit data delay
RDATDLY = 10 2-bit data delay
RDATDLY = 11 Reserved
RFIG
The McBSP can be configured to ignore transmit and receive frame-synchronization
pulses. The (R/X)FIG bit in (R/X)CR2 can be programmed to zero to
recognize frame-sync pulses, or set to one to ignore frame-sync pulses. The
user can use (R/X)FIG bit to either pack data or ignore unexpected frame-sync
pulses.
Structure of XCR1 and XCR2 is similar to that of RCR1 and RCR2.

24. McBSP Reset (R/X)RST and RESET
Device reset (RS = 0) places the receiver, transmitter and the sample rate generator SRGR in reset.
When the device reset is removed (RS = 1) GRST = FRST = RRST = XRST = 0, keeping the entire serial port in the reset state.
The SP transmitter and receiver can be independently reset by the RRST and XRST bits in the SPCR registers. The SRGR is reset by the GRST bit in SPCR2.

25. Determining Ready Status
RRDY and XRDY indicate the ready state of the McBSP receiver and transmitter.
Serial port writes and reads may be synchronized:
By polling RRDY and XRDY,
or by using the events to DMA
REVT and XEVT in normal mode,
and REVTA and XEVTA in A-bis mode,
or by interrupts to CPU (RINT and XINT), which the events generate.
Note that reading DRR[1,2] and writing to DXR[1,2] affect RRDY and XRDY.
Receive Ready Status: REVT, RINT, and RRDY
RRDY = 1 indicates that the RBR[1,2] contents have been copied to DRR[1,2]
and that the data can be read by the CPU or DMA. Once that data has been
read by either the CPU or DMA, RRDY is cleared to 0. Also, at device reset
or serial port receiver reset (RRST = 0), RRDY is cleared to 0 to indicate no
data has yet been received and loaded into DRR[1,2]. RRDY directly drives
the McBSP receive event to the DMA (REVT). Also, the McBSP receive interrupt
(RINT) to the CPU may be driven by RRDY, if RINTM = 00b in SPCR1.
Transmit Ready Status: XEVT, XINT, and XRDY
XRDY = 1 indicates that the DXR[1,2] contents have been copied to XSR[1,2]
and that DXR[1,2] is ready to be loaded with a new data word. When the transmitter
transitions from reset to non-reset (XRST transitions from 0 to 1), XRDY
also transitions from 0 to 1 indicating that DXR[1,2] is ready for new data. Once
new data is loaded by the CPU or DMA, XRDY is cleared to 0. However, once
this data is copied from DXR[1,2] to XSR[1,2], XRDY transitions again from 0
to 1. Now once again, the CPU or DMA can write to DXR[1,2] although
XSR[1,2] has not been shifted out on DX yet. XRDY directly drives the transmit
synchronization event to the DMA (XEVT or XEVTA). In addition, the transmit
interrupt (XINT) to the CPU may also be driven by XRDY, if XINTM = 00b in
SPCR2.

26. Frame and Clock Configuration
The McBSP allows independent configurations of data clock and frame synchronization for receive and transmit:
Polarities of FSR, FSX, CLKX, and CLKR
A choice of single- or dual-phase frames
For each phase, the number of words per frame
For each phase, the number of bits per word
Subsequent frame synchronization may restart the serial data stream or be ignored.
The data bit delay from frame synchronization to first data bit can be 0-,
1-, or 2-bit delays.
Right- or left-justification as well as sign-extension or zero-filling can be chosen for receive data.
Serial clocks CLKR, and CLKX define the boundaries between bits for
receive and transmit, respectively. Similarly, frame-sync signals FSR and FSX
define the beginning of a serial word.

27. Frame and Clock Operation
Receive and transmit frame-sync pulses can be generated:
Either internally by the sample rate generator SRGR,
or driven by an external source.
The source of frame sync is selected by the mode bit, FS(R/X)M, in the PCR.
FSR is affected by GSYNC bit in SRGR2
Receive and transmit clocks can be selected to be inputs or outputs by the mode bit, CLK(R/X)M, in the PCR.
Receive and transmit frame-sync pulses can be generated either internally by
the sample rate generator (see section 2.5.1, Sample Rate Generator Clocking
and Framing, on page 2-58) or driven by an external source. The source
of frame sync is selected by programming the mode bit, FS(R/X)M, in the PCR.
FSR is also affected by the GSYNC bit in SRGR2 (for details, see section
, Receive Frame-Sync Selection: DLB, FSRM, GSYNC, on page 2-67).
Similarly, receive and transmit clocks can be selected to be inputs or outputs
by programming the mode bit, CLK(R/X)M, in the PCR.
When FSR and FSX are inputs (FSXM=FSRM=0, external frame-sync
pulses), the McBSP detects them on the internal falling edge of clock, internal
CLKR, and internal CLKX, respectively (see Figure 2–41, Clock and Frame
Generation, on page 2-57). The receive data arriving at the DR pin is also
sampled on the falling edge of internal CLKR. Note that these internal clock
signals are either derived from external source via CLK(R/X) pins or driven by
the sample rate generator clock (CLKG) internal to the McBSP.

28. Sample Rate Generator
The sample rate generator is composed of a three-stage clock divider that allows
programmable data clocks (CLKG) and framing signals (FSG).
CLKG and FSG are McBSP internal signals that can be programmed
to drive receive and/or transmit clocking (CLKR/X) and framing (FSR/X).
The sample rate generator can be programmed to be driven by an
internal clock source or an internal clock derived from an external clock source.
The three stages of the sample rate generator circuit compute the following:
- Clock divide down (CLKGDV): The number of input clocks per data bit clock.
- Frame period divide down (FPER): The frame period in data bit-clocks.
- Frame width count down (FWID): The width of an active frame pulse in
data bit-clocks.
In addition, a frame pulse detection and clock synchronization module allows
synchronization of the clock divide down with an incoming frame pulse.

29. Sample Rate Generator Register SRGR
FWID = Frame Width
CLKGDV = Sample rate generator Clock Divider
SRGR 2
GSYNC = SRGR Clock synchronization
CLKSP = Polarity Clock edge selection
CLKSM = SRGR Clock Mode
FSGM = SRGR transmit Frame-Sync Mode
FPER = Frame Period
SRGR1
FWID Frame Width.
This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period.
Range: up to 2; 1 to 256 CLKG periods.
CLKGDV Sample Rate Generator Clock Divider
This value is used as the divide-down number to generate the required
sample rate generator clock frequency. Default value is 1.
SRGR2
GSYNC Sample Rate Generator Clock Synchronization
Only used when the external clock (CLKS) drives the sample rate generator
clock (CLKSM=0).
GSYNC = 0 The sample rate generator clock (CLKG) is free running.
GSYNC = 1 The sample rate generator clock (CLKG) is running. But
CLKG is resynchronized and frame-sync signal (FSG) is
generated only after detecting the receive
frame-synchronization signal (FSR). Also, frame period,
FPER, is a don’t care because the period is dictated by the
external frame-sync pulse.
CLKSP CLKS Polarity Clock Edge Select
Only used when the external clock CLKS drives the sample rate generator
clock (CLKSM = 0).
CLKSP = 0 Rising edge of CLKS generates CLKG and FSG.
CLKSP = 1 Falling edge of CLKS generates CLKG and FSG.
CLKSM McBSP Sample Rate Generator Clock Mode
CLKSM = 0 Sample rate generator clock derived from the CLKS pin.
CLKSM = 1 Sample rate generator clock derived from CPU clock.
FSGM Sample Rate Generator Transmit Frame-Synchronization Mode
Used when FSXM=1 in the PCR.
FSGM = 0 Transmit frame-sync signal (FSX) due to
DXR[1,2]-to-XSR[1,2] copy. When FSGM = 0, FPR and
FWID are ignored.
FSGM = 1 Transmit frame-sync signal driven by the sample rate
generator frame-sync signal, FSG.
FPER Frame Period. This field plus 1 determines when the next frame-sync signal
becomes active.
Range: 1 to 4096 CLKG periods.

30. Data Clock Generation
When (CLK[R/X]M = 1), the data clocks (CLK[R/X]) are driven by:
the internal SRGR output clock, CLKG.
The input clock to the SRGR can be either the CPU clock or a dedicated external clock input (CLKS).
The CLKSM bit in SRGR2 selects either the CPU clock (CLKSM = 1) or the external clock input (CLKSM = 0) CLKS.
The input clock source to the SRGR can be divided down by a programmable value (CLKGDV) to drive CLKG
Regardless of the source to the SRGR, the rising edge of CLKSRG generates CLKG and FSG
Sample Rate Generator Data Bit Clock Rate: CLKGDV
The first divider stage generates the serial data bit clock from the input clock.
This divider stage utilizes a counter that is preloaded by CLKGDV which contains
the divide ratio value. The output of this stage is the data bit-clock which
is output on sample rate generator output, CLKG, and serves as the input for
the second and third divider stages.
CLKG has a frequency equal to 1/(CLKGDV+1) of sample rate generator input
clock. Thus, sample generator input clock frequency is divided by a value between
1 and 256. When CLKGDV is odd or equal to 0, the CLKG duty cycle
is 50%. When CLKGDV is an even value, 2p, representing an odd divide down,
the high-state duration is p+1 cycles and the low-state duration is p
cycles.
Bit Clock Polarity: CLKSP
External clock (CLKS) is selected to drive the sample rate generator clock divider
by selecting CLKSM=0. In this case, the CLKSP bit in SRGR2 selects the
edge of CLKS on which sample rate generator data bit-clock (CLKG) and
frame-sync signal (FSG) are generated. Since the rising edge of CLKSRG
(see Figure 2–42) generates CLKG and FSG, the rising edge of CLKS when
CLKSP = 0, or the falling edge of CLKS when CLKSP = 1, causes the transition
on the data bit-rate clock (CLKG) and frame sync (FSG).
Bit Clock and Frame Synchronization
When CLKS is selected to drive the sample rate generator (CLKSM = 0),
GSYNC can be used to configure the timing of CLKG relative to CLKS.
GSYNC = 1 ensures that the McBSP, and the external device that it is communicating
to, are dividing down CLKS with the same phase relationship. If
GSYNC = 0, this feature is disabled and therefore CLKG runs freely and is not
re-synchronized. If GSYNC = 1, an inactive-to-active transition on FSR triggers
a resynchronization of CLKG and generation of FSG. CLKG always begins
with a high state after synchronization. Also, FSR is always detected at
the same edge of CLKS that generates CLKG, no matter how long the FSR
pulse is. Although an external FSR is provided, FSG can still drive internal receive
frame synchronization when GSYNC = 1. Note that when GSYNC = 1,
FPER is a don’t care because the frame period is determined by the arrival of
the external frame-sync pulse.
Figure 2–45 and Figure 2–46 show the bit clock and frame-synchronization
operation with various polarities of CLKS and FSR. These figures assume
FWID = 0, for an FSG one CLKG wide.

31. Digital Loop Back Mode DLB
DLB = 1 in SPCR1 enables digital loop back mode.
During DLB mode, DR, FSR, and CLKR are internally connected through multiplexers to DX, FSX, CLKX, respectively.
DLB mode allows testing of serial port code with a single DSP device.
In digital loop back mode, the transmitter clock drives the receiver. CLKRM determines whether the CLKR pin is an input or an output.

32. Frame-sync Signal Generation
When FRST=1 in SPCR2, it activates the frame-sync generation logic to generate a frame-sync signal, if FSGM = 1 in SRGR2.
Frame-sync programming options:
A frame pulse with a programmable period and programmable active width, using the SRGR1 register,
The transmit portion may trigger its own frame-sync signal generated by a DXR[1,2]-to-XSR[1,2] copy,
Both the receive and transmit sections may independently select an external frame synchronization on the FSR and FSX pins, respectively.
When the transmit portion triggers its own frame-sync signal generated by
a DXR[1,2]-to-XSR[1,2] copy. the data delays can be programmed as required;
however, maximum frame frequency cannot be achieved in this method
for data delays one and two. This limitation can be overcome by programming
the frame ignore bit (R/X)FIG = 1.
Frame Period and Frame Width: FPER and FWID
FPER and FWID are implemented as down-counters. The FPER stage is a
12-bit down-counter that counts down the generated data clocks from 4095 to
0. FPER controls the period of active frame-sync pulses. The FWID stage in
the sample rate generator is an 8-bit down counter. The FWID field controls
the active width of the frame-sync pulse. Both these counters gets loaded with
their respective programmed value in FPER and FWID.
When the sample rate generator comes out of reset, FSG is in its inactive state.
Then, when FRST = 1 and FSGM = 1, a frame sync is generated. The frame
width value (FWID+1) is counted down on every CLKG cycle until it reaches
zero, when FSG goes low. Thus, the value of FWID + 1 determines an active
frame pulse width ranging from 1 to 256 data bit-clocks. At the same time, the
frame period value (FPER+1) is also counting down. When this value reaches
zero, FSG goes high, again indicating a new frame.
It is recommended that FWID be programmed to a value less than
WDLEN[1,2].Thus, the value of FPER+1 determines a frame length from 1 to
4096 data bits. When GSYNC = 1, FPER is a don’t care value. Figure 2–47
shows a frame of period 16 CLKG periods (FPER = 15 or b), and a
frame with an active width of 2 CLKG periods (FWID = 1).

33. McBSP - Example
Problem: transfer bit words to SARAM, ext’l CLK/FS, no CPU int
Operation
- Bit/CLKR shifted into RSR
- RSR  RBR
- RBR  DRR (RRDY=1)
- REVT sync event activates DMA (no McBSP setup)
- DMA transfers DRR to SARAM
…repeat

34. Multichannel Selection Operation
A McBSP channel is a time slot for shifting in/out the bits of one serial word.
Each McBSP supports up to 128 channels.
The 128 channels are divided into 8 blocks of 16 consecutive channels:
Block 0: Channels 0-15
Block 1: Channels …
Block 7: Channels
The blocks are assigned to partitions:
In ‘C5410 or ‘C5420, only 2 partitions A or B
In the C5416 and C5510, choice between 2 partitions (A,B) or 8 partitions (A, B, C, …H.)
Multiple channels can be independently selected for the transmitter and receiver
by configuring the McBSP with a single-phase frame. Each frame represents
a time-division multiplexed (TDM) data stream. The number of words per
frame represented by (R/X)FRLEN1, denotes the number of channels available
for selection.
When using TDM data streams, the CPU may need to process only a few of
them. Thus, to save memory and bus bandwidth, multichannel selection allows
independent enabling of particular channels for transmission and reception.
Up to 32 channels can be enabled in an up-to-128-channel bit-stream.

35. Multichannel Partition Mode
In the 2 partitions mode:
One even-numbered block (0,2,4,6) is assigned to partition A and one odd-numbered block (1,3,5,7) to partition B.
Up to 32 channels can be selected.
In the 8 partitions mode, blocks 0 through 7 are automatically assigned to partitions A through H.
Up to 128 channels can be selected.
The number of partitions for reception and transmission are independent.

36. Multichannel Selection
When a McBSP uses a TDM (Time Division Multiplex) data stream, it may need to select only a few channels to save memory and bandwidth.
Each channel partition has a dedicated channel enable register.
If the multichannel selection mode is on, each bit in the register controls whether a channel is selected or not in the partition.
There is 1 receive multichannel selection mode and 3 transmit modes.

37. Configuring a Frame for Multichannel Selection
Select a single-phase frame:
RPHASE/WPHASE = 0
Each frame represents a TDM data stream.
Set a frame length (R/X)FRLEN1 including the highest-numbered channel in the selection.

38. Control of Multichannel Selection
The multichannel mode can be enabled independently for receive and transmit by setting RMCM = 1 and XMCM to a non-zero value in control registers MCR[1,2], respectively.
Choose the partition mode: 2 or 8 partitions, with the RMCME and/or XMCME bits:
(R/X)MCME = 0, 2 partitions A-B
(R/X)MCME = 1, 8 partitions A-B…H

39. Multichannel Operation Control Registers
MCR1, MCR2: Multichannel control registers
XCERx: transmit channel enable registers
x = a letter A, B, C, D, E, F or H
RCERx: receive channel enable registers

40. Multichannel Operation MCR1 Register
MCR1 for C5410 or C5420
RPBBLK = Receive Partition B Block
RPABLK = Receive Partition A Block
RCBLK = Receive Current Block
RMCM = Receive Multichannel Selection Enable
MCR1 for C5416 and C5510
RMCME = Receive Multichannel Partition Mode bit, applicable if channel can be individually selected RMCM = 1
MCR1
RPBBLK Receive Partition B Block
RPBBLK = 00 Block 1. Channel 16 to channel 31
RPBBLK = 01 Block 3. Channel 48 to channel 63
RPBBLK = 10 Block 5. Channel 80 to channel 95
RPBBLK = 11 Block 7. Channel 112 to channel 127
RPABLK Receive Partition A Block
RPABLK = 00 Block 0. Channel 0 to channel 15
RPABLK = 01 Block 2. Channel 32 to channel 47
RPABLK = 10 Block 4. Channel 64 to channel 79
RPABLK = 11 Block 6. Channel 96 to channel 111
RCBLK Receive Current Block
RCBLK = 000 Block 0. Channel 0 to channel 15
RCBLK = 001 Block 1. Channel 16 to channel 31
RCBLK = 010 Block 2. Channel 32 to channel 47
RCBLK = 011 Block 3. Channel 48 to channel 63
RCBLK = 100 Block 4. Channel 64 to channel 79
RCBLK = 101 Block 5. Channel 80 to channel 95
RCBLK = 110 Block 6. Channel 96 to channel 111
RCBLK = 111 Block 7. Channel 112 to channel 127
RMCM Receive Multichannel Selection Enable
RMCM = 0 All 128 channels enabled.
RMCM = 1 All channels disabled by default. Required channels are
selected by enabling RP(A/B)BLK and RCER(A/B) appropriately.
RMCME Receive multichannel partition mode bit. RMCME is only applicable if channels
can be individually enabled or disabled for reception (RMCM = 1).
RMCME determines whether only 32 channels or all 128 channels are to
be individually selectable.
0 2-partition mode
Only partitions A and B are used. You can control up to 32 channels in the
receive multichannel selection mode (RMCM = 1).
Assign 16 channels to partition A with the RPABLK bits. Assign 16 channels
to partition B with the RPBBLK bits.
You control the channels with the appropriate receive channel enable registers:
RCERA: Channels in partition A
RCERB: Channels in partition B
1 8-partition mode
All partitions (A through H) are used. You can control up to 128 channels in
the receive multichannel selection mode.
RCERA: Channels 0 through 15
RCERB: Channels 16 through 31
RCERC: Channels 32 through 47
RCERD: Channels 48 through 63
RCERE: Channels 64 through 79
RCERF: Channels 80 through 95
RCERG: Channels 96 through 111
RCERH: Channels 112 through 127

41. Multichannel Operation MCR2 Register
MCR2 has the same structure as MCR1 but for transmission.
MCR 2 for C5410 or C54 20
MCR 2 for C5416 and C5510
The XMCM bits of XCR2 determine whether all channels or only selected channels are enabled and unmasked for transmission.
There are 3 transmit multichannel selection modes
00b: No selection. All channels are enabled and unmasked.
01b: All channels are disabled unless selected in XCERs registers. If enabled, a channel is also unmasked.
10b: All channels are enabled, but they are masked unless they are selected in XCERs registers.
11 b: symmetric transmission/reception. All channels are disabled for transmission unless they are enabled for reception in RCER registers. Once enabled, they are masked unless they are also selected in the XCERs registers.
XMCM Transmit Multichannel Selection Enable
XMCM = 00 All channels enabled without masking (DX is always
driven during transmission of data
XMCM = 01 All channels disabled and therefore masked by default.
Required channels are selected by enabling XP(A/B)BLK
and XCER(A/B) appropriately. Also, these selected
channels are not masked and therefore DX is always
driven.
XMCM = 10 All channels enabled, but masked. Selected channels
enabled via XP(A/B)BLK and XCER(A/B) are unmasked.
XMCM = 11 All channels disabled and therefore masked by default.
Required channels are selected by enabling
RP(A/B)BLK and RCER(A/B) appropriately. Selected
channels can be unmasked by RP(A/B)BLK and
XCER(A/B). This mode is used for symmetric transmit
and receive operation.
† DX is masked or driven to hi-Z during (a) interpacket intervals, (b) when a channel is masked regardless of whether it is enabled,
or (c) when a channel is disabled.

42. Using 2 partitions A and B
McBSP channels are activated using an alternating scheme. After a sync pulse:
Receiver or transmitter begins with the channels in partition A and alternates between part. B and A until the end of the frame.
Assigning blocks to partitions. Any 2 of the 8 blocks can be assigned to A and B:
Assign an even-numbered block to A by writing the 2 (R/X)PABLK bits and an odd-numbered block to B (R/X)PBBLK.
The channels are controlled the receive or transmit channel enable registers (R/X)CERCA, (R/X)CERA.

43. Using 2 partitions A and B
Blocks can be reassigned during communication if we want to use more than 32 selected channels.
It is not possible to modify the block assignment of a partition during its transfer.
The block currently involved in the transmission is reflected in the (R/X)CBLK bits. They can be polled.
At the end of a block, an interrupt can be sent to the CPU that checks (R/X)CBLK bits and updates the inactive partition.

44. Using 8 Partitions RMCME/XMCME = 1
Partitions are activated in the order:
A B C D E F G H.
The (R/X)PABLK and (R/X)PBBLK are ignored.
The blocks are assigned to the partitions in natural order:
A: block 0, channels 0 to 15, reg. (R/X)CERA
B: block 1, channels 16 to 31, reg. (R/X)CERB …
H: block 7, chan. 112 to 127, reg. (R/X)CERH

45. Receive Channels Disabled
If a receive channel is disabled, any bits received in that channel are passed only as far as the receive buffer register(s) (RBR(s)).
The receiver does not copy the content of the RBR(s) to the DRR(s), and as a result, does not set the receiver ready bit (RRDY).
Therefore, no DMA synchronization event (REVT) is generated, and if the receiver interrupt mode depends on RRDY (RINTM = 00b), no interrupt is generated.

46. Enabling/Disabling versus Masking/Unmasking
For transmission, a channel may be:
Enabled and unmasked
Transmission can begin and be completed
Enabled: Data are passed from DXR to XSR.
Unmasked: Data in XSR shifted out on DX pin.
Enabled and masked
Transmission can begin but cannot be completed
Masked: DX pin is held in high impedance. Avoids bus contention on a shared serial bus.
Disabled
Transmission cannot occur. No DXR to XSR copy.
The bit XRDY is not set.

47. Channel Enable Registers RCERx and XCERx
In C5410 and C5420, there are 2 receive and 2 transmit Channel Enable Registers: RCERA, RCERB, XCERA, XCERB.
In C5416 and C5510, there are 8 receive + 8 transmit Channel Enable Registers: RCERA to RCERH and XCERA to XCERH.
RCERA
XCERA
RCEA(0:15) Receive Channel Enable-
RCEA n= 0 Disables reception of nth channel in an even-numbered block in partition A
RCEA n= 1 Enables reception of nth channel in an even-numbered block in partition A

48. SPI Mode
The SPI protocol is a master-slave configuration, with one master device and one or more slave devices. The interface consists of four signals.
The clock stop mode of the McBSP provides compatibility with the SPI protocol.

49. McBSP Pins as General Purpose I/O pins 1 of 2
Two conditions allow the serial port pins (CLKX, FSX, DX, CLKR, FSR and DR) to be used as general purpose input/output (I/O) rather than serial port pins:
1) The related portion (transmitter or receiver) of the serial port is in reset; (R/X)RST = 0 in SPCR[1,2].
2) General purpose I/O is enabled for the related portion of the serial port; (R/X)IOEN = 1 in the PCR.
In the case of FS(R/X), FS(R/X)M=0(or 1) configures the pin as an input (or output).
When configured as an output, the value driven on FS(R/X) is the value stored in FS(R/X)P.
If configured as an input, FS(R/X)P becomes a read-only bit that reflects the status of that signal.

50. McBSP Pins as General Purpose I/O pins 2 of 2
CLK(R/X)M and CLK(R/X)P work similarly for CLK(R/X).
DX and DR as GPIO pins:
the value of the DX_STAT bit in the PCR is driven onto DX.
DR is always an input and its value is held in the DR_STAT bit in the PCR.
CLKS as a general purpose input:
both the transmitter and receiver must be in reset state and (R/X)IOEN = 1, because CLKS is always an input to the McBSP and affects both transmit and receive operations.

51. McBSP Operation in Power-down Mode
For the C5416, Power-down modes may be invoked in several ways:
executing the IDLE instruction or driving the HOLD input low with the HM status bit set to one.
The McBSP can take the CPU out of IDLE using a transmit or receive interrupt.
When in IDLE1 or HOLD modes, the McBSP continues to operate normally with no restrictions.
In IDLE2 or IDLE3 modes, the internal device clocks provided to the peripherals are stopped.
If external clock and frame-sync are provided, the McBSP can continue to operate, and receive and transmit interrupts can be used to exit the IDLE state.
If either clocks or frame-syncs are internal, the McBSP will stop in IDLE2/3.
In IDLE2/3, the internal clocks to the McBSP and the DMA controller are started automatically when a transfer begins, and stopped after the transferis completed.

52. McBSP Operation in Power-down Mode
For the C5510, The McBSP is placed into its idle mode when:
the PERIPH idle domain is idle (PERIS = 1 in ISTR)
the McBSP idle enable bit is set (SPn = 1) in the PICR register. When the McBSP is in the Idle state, it is unable to receive or transmit data.
In the McBSP idle mode:
If the McBSP is operates with internal clocking and frame sync., it will be completely stopped.
If the McBSP is operates with ext. clocking and frame sync., the external interface portion of the McBSP continues to function during external clock activity periods. The McBSP sends a request to activate the PERIPH and DMA idle domains when it needs to be serviced. If the domains were idle, they are made idle again after the McBSP has been serviced.

53. Emulation FREE and SOFT Bits
FREE and SOFT are special emulation bits that determine the state of the serial port clock when a breakpoint is encountered in the high-level language debugger.
If the FREE bit is set to 1
upon a software breakpoint, the clock continues to run (free runs) and data still shifts out. When FREE = 1, the SOFT bit is a don’t care.
If the FREE bit is cleared to zero, then the SOFT bit takes effect.
If the SOFT bit is cleared to zero, then the clock stops immediately, thus aborting a transmission.
If the SOFT bit is set to one and a transmission is in progress, the transmission continues until completion of the transfer, and then the clock halts.
The receiver-side functions in a similar fashion.

54. Differences Between C5416 and C5510 McBSP
Addressing of McBSP registers:
C5416: sub-bank system
Some registers are mapped in data memory page 0: DRR, DXR + SPSA and SPSD
SPSAx: McBSP Sub-Address register associated with a SPSD Sub-bank Data register containing the value for one of the sub-bank registers
The other registers are sub-bank registers accessed by sub-addresses relative to SPSA.
C5510: Registers are mapped in the I/O space
Power-down modes
C5416 McBSP
Registers addr.

55. Configuration of the McBSP 1 of 3
Receiver/transmitter configuration
Place the McBSP receiver / transmitter in reset
Program the McBSP registers for the desired receiver / transmitter operation
Take the receiver / transmitter out of reset

56. Configuration of the McBSP 2 of 3
Global behavior
Set the receiver pins to operate as McBSP pins
Enable/disable the digital loopback mode
Enable/disable the clock stop mode
Enable/disable the receive multichannel selection mode
Data behavior
Choose 1 or 2 phases for the receive frame
Set the receive word length(s)
Set the receive frame length
Enable/disable the receive frame-sync ignore function
Set the receive companding mode
Set the receive data delay
Set the receive sign-extension and justification mode
Set the receive interrupt mode

57. Configuration of the McBSP 3 of 3
Frame-sync behavior
Set the receive frame-sync mode
Set the receive frame-sync polarity
Set the SRG frame-sync period and pulse width
Clock behavior
Set the receive clock mode
Set the receive clock polarity
Set the SRG clock divide-down value
Set the SRG clock synchronization mode
Set the SRG clock mode [choose an input clock]
Set the SRG input clock polarity

58. Configuration of the McBSP with CSL
Example of the DSK-CCS tutorial audioIO.c of Chapter 4 for the ‘C5416.
First we examine the file audioIOcfg_c.c that configures the DSP,
Then we explain how to automatically generate it with the GUI interface of CCS.
Parameters:
The McBSP 2 is used
Single phase mode
32 bits words.
List of files of the example to examine
audioIOcfg.h
audioIOcfg_c.c

59. File audioIOcfg.h Includes the Chip Support Library for the McBSP
Defines variables

60. Example of McBSP configuration file 1st part of the file audioIOcfg_c
Example of McBSP configuration file 1st part of the file audioIOcfg_c.c
SPCR1=0, SPCR2=0x200
RCR1=0x00a0, RCR2=0
XCR1=0x00a0, XCR2=0
SRGR1=0x1f00, SRGR2=0x003f
MCR1=0x0000, MCR2=0x0000
PCR=0x0083
All receive channel enable registers RCERx are set to 0

61. Example of McBSP Configuration File Last Part of the File
All transmit channel enable registers XCERx are set to 0
Using CSL to open and initialise the McBSP 2.

62. File audioIOcfg_c.c 1 of 3
SPCR1 = 0, SPCR2 = 0x0200, Serial Port Control Registers
RJUST=0, CLKSTP=0, DXENA=0, RINTM=0, RSYNCERR=0, RRST=0
FREE=1, SOFT=0, FRST=GRST=XINTM=XSYNCERR,XRST=0
RCR1 = 0x00A0, RCR2 = 0, Receive Control Registers
RWDLEN1=101 = 32 bits words, RFLEN1=0 = 1 word per frame
RDATDLY=0, 0 bit data delay
RFIG=0, received frame-sync not ignored
RCOMPAND=0, no companding
RWLEN2=0
RFRLEN2= 0
RPHASE = 0 = 1 phase per frame, RWLEN2 and RFRLEN2 ignored.
XCR1 = 0x00A0, XCR2 =0 same remarks as for RCR, Transmit Control Register.

63. File audioIOcfg_c.c 2 of 3
SRGR1 = 0x1F00, SRGR2 = 0x003F, Sample Rate Generator Registers
CLKGDV =0, divide down value for CLKG
FWID = 0x1F=31, frame-sync pulse width for FSG = 32 CLKG cycles
FPER=0x3F=63, Frame-sync period bits for FSG, the period between frame-sync pulses on FSG is 64 CLKG cycles.
FSGM=0, if FSXM=1 in PCR, the McBSP generates a frame-sync pulse when DXR is copied in XSR. But here FSXM=0 (see PCR).
CLKSM=0, the input clock for SRGR is taken on CLKS pin or CLKR pin depending on SCLKME bit in PCR. Here SCLKME=1=signal on CLKR.
CLKSP=0, CLKS pin polarity, the rising edge on CLKS pin drives the clock signal CLKG and FSG.
GSYNC=0, no clock synchronization
MCR1 = 0, MCR2 = 0, no multichannel selection, Multichannel Control Registers

64. File audioIOcfg_c.c 3 of 3 PCR = 0x0083, Pin control Register
CLKRP=1, CLKXP=1, clock polarity
As CLKRM=0, CLKR is an input and the received data is sampled on the rising edge of CLKR.
transmit data is driven on falling edge of CLKX.
FSRP=FSXP=0, frame-sync pulses are active high.
DRSTAT=0, DXSTAT=0, not applicable here.
CLKSTAT=0,not applicable here.
SCLKME=1, SRGR input clock is taken from CLKR pin (CLKSM=0).
CLKRM=CLKXM=0, not in DLB so the CLKR and CLKX pins are inputs that suppies the internal clocks.
FSRM=FSXM=0, Receive and transmit frame-sync is supplied by an ext source via FSR and FSX pins.
RIOEN=XIOEN=0, the McBSP pins are not GPIO pins
IDLEEN=0, the McBSP remains active when the PERIPH domain is idled.
RCERx and XCREx = 0, There is no multichannel selection

65. Example using the ‘C5416 DSK 1 of 2
Create a new project iomcbsp.pjt and Create a new cdb file

66. Example using the ‘C5416 DSK 2 of 2
Save (File>Save) the new configuration file under the project directory: iomcbsp.cdb
Add to the project two of the files generated at the previous step: the configuration file (*.cdb) and the linker command file (*.cmd).
Copy the file audioIO.c of chapter ‘ example in the project directory and rename it iomcbsp.c
Modify the main source file: iomcbsp to include the header file iomcbspcfg.h generated at the configuration step
and add iomcbsp.c to the project.
Modify build options:
Project>Build Options to add the dsk5416f.lib library and set use far calls.

67. Configuring the McBSP using the McBSP Configuration Manager of the CSL GUI

68. Configuring the McBSP using the CSL GUI 1 of 4

69. Configuring the McBSP using the CSL GUI 2 of 4

70. Configuring the McBSP using the CSL GUI 3 of 4

71. Configuring the McBSP using the CSL GUI 4 of 4
Modify:
« Receive Lengths », « Transmit Lengths » to set word length to 32 bits
« Sample_Rate Gen »,
choose generator clock source=BCLKR
set frame width to 32 and frame period to 64.
« Transmit Mode », clock polarity = falling edge
« General »
Set Breakpoint Emulation to do not stop to set FREE = 1.
Save the new iomcbsp.cdb file and look at the iomcbspcfg_c.c file. It should be quite similar to the audioIOcfg_c.c file for the initialization part.

72. View of iomcbspcfg_c.c file at this Step

73. Configuring the McBSP using the Resource Manager of the CSL GUI
Use the McBSP Resource Manager menu to generate the MCBSP_open()and the MCBSP_config() CSL functions.
It allows to select, open, initialize a device
We select McBSP 2
We ask for the McBSP handle creation with the name C54XX_DMA_MCBSP that will be used by the routines of the BSL.
And we ask for the opening of the McBSP handle and for the pre-initialization with object mcbspCfg0.

74. Configuring the McBSP using the CSL GUI 1 of 4

75. Configuring the McBSP using the CSL GUI 2 of 4

76. Configuring the McBSP using the CSL GUI 3 of 4

77. Configuring the McBSP using the CSL GUI 4 of 4
Save the file iomcbsp.cdb
Open the file iomcbspcfg_c.c
You should see the instructions for the opening and initialization of the McBSP.

78. Final version of the iomcbspcfg_c.c File
Creation of the McBSP handle
Opening and initialization of McBSP2

79. Test the iomcbsp program
Build the project
Load iomcbsp.out in Program memory
Check the program
using a microphone (or a CD output) and earphones, you should hear the input (mike or CD) in the earphones (or loudspeaker).
Use tools>C54xx McBSP to view all the registers of the McBSP.

80. References User’s guides Spru302: Tms320c5416.pdf Spru592a:
TMS320C54x DSP Reference Set Volume 5: Enhanced Peripherals.
Tms320c5416.pdf
Spru592a:
TMS320VC5501/5502/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide.