1. new ps TDC for HEP and other applications
Jorgen Christiansen, Moritz Horstmann, Lukas Perktold (Now AMS), Jeffrey Prinzie (Leuven)
CERN/PH-ESE

2. Time Measurement Chain
Detector and discriminator critical and must be optimized together
Arrival time +
Time over threshold (Amplitude)

3. TDC applications in HEP
Large systems with many channels: 10k-100k:
Global time resolution/stability across large system critical
Drift time in gas based tracking detectors
Low resolution: ~1ns
Examples: CMS, ATLAS, LHCb, PANDA drift tubes
TOF, RICH
High resolution: 5 – 100ps
Example: ALICE TOF
Background reduction: 5 – 10ps
Vertex identification from timing: ps
Signal amplitude and time walk compensation: Time Over Threshold (TOT)
Or constant fraction discrimination in analog FE
Triggered or non triggered
New TDC with programmable resolution: 3ps, 12ps, (400ps ?)
Power consumption highly resolution dependent

4. Other TDC applications
Laser ranging
3D imaging
Medical imaging: TOF PET
Improve signal/noise, lower radiation
Fluorescence lifetime imaging
General instrumentation.
Differences to HEP systems
Small systems - Few channels
Time resolution/stability between channels on same chip
Averaging can in many cases be used to get improved time resolution

5. HPTDC History Features Used in large number of applications:
Architecture developed for CERN for ATLAS MDT with final design transferred to Japan
CMS Muon and ALICE TOF needed similar chip with additional features/ increased time resolution
Features
32 channels(100ps binning), 8 channels (25ps binning)
40MHz time reference (LHC clock)
Leading, trailing edge and time over threshold (Time walk correction)
Triggered or non triggered
Highly flexible data driven architecture with extensive data buffering and different readout interfaces
Used in large number of applications:
More than 20 HEP applications: ALICE TOF, CMS muon, STAR, BES, KABES, HADES, NICA, NA62, AMS, Belle, BES, , ,
We still sell ~1k chips per year from current stock.
Other research domains: Medical imaging,
Commercial modules from 3 companies: CAEN, Cronologic, Bluesky
~50k chips produced
250nm technology (~10 years ago for LHC)
Development: ~5 man-years + 500kCHF.
manual_ver2.2.pdf
17ps RMS

6. New detectors and sensors require new TDC
TDC Trends
integration
resolution
3ps binning (1-2ps RMS)
High integration
Flexible
New detectors and sensors require new TDC

7. TDC architecture prototyped in 130nm
Counter
External time reference (clock).
3 stage time measurement:
Counter: 800ps, Delay locked loop: 25ps, Resistive interpolation: 6.25ps
Can be scaled to the number of channels required.
Prototyped in 130nm CMOS and extensively characterized by Lukas Perktold.
Measured time resolution: 2.5ps RMS

8. Resistive Interpolation
Resistive voltage divider -> Signal slopes lager than delay stabilized by DLL
RC delay (capacitive loading) - > Small resistances, small loads
- > Simulation based optimization of resistor values

9. INL = ± 1.3 LSB RMS = < 0.43 LSB (2.2 ps)
Measured performance
INL = ± 1.3 LSB RMS = < 0.43 LSB (2.2 ps)
Expected rms resolution from circuit simulations: including quantization noise, INL & DNL
2.3 ps-rms < σqDNL/wINL < 2.9 ps-rms

10. L. Perktold / J. Christiansen
Single Shot Precision
Three measurement series - Both hits arrive within one reference clock cycle - Second hit arrives one clock cycle later - Second hit arrives multiple clock cycles later (~5ns)
bin difference
σTDC < ps-rms
TWEPP2013 slides and paper:
ESE seminar:
TWEPP 2013
L. Perktold / J. Christiansen

11. Mapping to 65nm Uncertain long term availability of IBM 130nm
2x time performance: -> 3ps binning
Lower power consumption: < ~½
~1/8 if DLL binning of 12ps enough. (6ps in 130nm with resistive interpolation)
Larger data buffers
More channels
Smaller chip
But higher development costs
MPW prototyping: ~80k
NRE for production masks: ~500k Find other project for shared production masks

12. Timing Generator (12 ps DLL, 3ps res int)
Full ps TDC ASIC
Timing Generator (12 ps DLL, 3ps res int)
PLL
Channels: 64
Binning: 3ps, 12ps, (400ps)
Reference: 40MHz clock
Leading, trailing, pairing edges
Hit rate: < 320MHz/channel
Data buffers per channel (512 hits per channel)
Triggered/un-triggered
Overlapping triggers
Flexible readout interface(s)
Power: 1 – ¼ W
40 MHz
64 Channels

13. Low jitter PLL
Clock multiplication from 40MHz to 2.56GHz for course time counter and time interpolator
Low jitter critical: < 1ps
Jitter filtering of 40MHz clock to the extent possible
40MHz reference MUST be very clean
LC based oscillator
Internal clock for logic and readout: 320MHz
Design: Jeffrey Prinzie, Leuven
Status/plans:
PLL circuit analysed and simulated at schematic level.
Detailed layout and optimization on-going
Dedicated prototype planned for Q (Synergy with LPGBT PLL)

14. Time interpolator and hit registers
Full custom layout in 65nm
Done (95%):
12ps binning DLL
3ps binning resistive interpolation
Ongoing:
Timing distribution in array
INL adjustment/correction
Hit register optimization:
Critical for power consumption: 64 x 128 = 8K hit registers clocked at 2.56GHz, plus time decoding pipeline ( total ~24K FF)
Pipelined time decoding
Time critical pipelined time decoding at 2.56GHz
Global layout integration, optimization and verification
Plan: Finalized ~end February
Designer: Mortiz Horstmann

15. TDC logic Synthesized logic from Verilog RTL
Based on data driven architecture from HPTDC
Simplifications as individual buffers per channel
Clocking: 320, 160, 80, 40 MHz
New features ?
Time reference channel65 ?
Trigger data path ?
Reuse of HPTDC verification environment
This is ~½ the design effort !.
New interfaces to be defined and implemented
Control/monitoring, Trigger, Readout
SEU/radiation tolerance
65nm technology TID tolerant
SEU detection and minimize effects from SEU when it can have major consequences (system sync)
As done in HPTDC
NOT RAD HARD
Planning:
Verilog code implementation and simulation: March – December 2015

16. Interfaces Power: 1.2v, < 1W Hits: Differential “LVDS”
Time reference: 40MHz “LVDS”
Other clock frequencies required ?.
Low jitter reference critical for high time resolution (especially for large systems time measurements across many channels/chips/modules)
IO signal levels: 1.2v or 2.5v ?
Trigger/BX-reset/reset: Sync Yes/No or encoded protocol ?
Control/monitoring: I2C ?
Readout: Formatting and signals ?
GBT E-link compatible: 320Mbits/s
1 – N bits
Parallel: 8, 16 or 32 40, 80, 160, 320 MHz
JTAG boundary scan + production test ?
Packaging: ~250 FPBGA

17. Schedule Interpolator circuit prototype: Done
Define final technology: Done
Final Specifications: Q1 2015
Finalize TDC macro: Q1 2015
PLL prototype: Q2 2015
Final RTL model: Q4 2015
P&R and Prototype submission: Q1 2016
Prototype test: Q2 2016
Final production masks/prototype: Q3 2016
Production lot: Q4 2016

18. Resources R&D Put in production 2-3 man-years chip design:
Main designer: Moritz Horstmann (new fellow)
Supervision: Jorgen Christiansen
PLL: Jeffrey Prinzie, Leuven (synergy LPGBT)
Low jitter/power differential input: Synergy with LPGBT
Contribution from others: Alberta ? , CAEN ?
RTL of interfaces
Chip testing, verification, characterization
~100k CHF prototyping, packaging, testing:
Put in production
~500k: NRE , Packaging, test
Cost sharing with other projects ?.
Funding from clients/users/projects required

19. Users/ clients No commercial TDC of this type available CERN HEP:
That’s the reason we have sold so many HPTDCs
CERN HEP:
TOTEM
CMS HPS and ATLAS FP420 (very forward detectors)
LHCb Torch (upgrade option)
CMS endcap Calorimeter with timing
ATLAS muon upgrade ? (low resolution)
Other HEP
Many experiments needs multi channel high/low resolution TDC
Many would like to explore ps timing as new “dimension” in HEP experiments. Detector and analog FE critical (e.g. CFD)
Non HEP research
Medical imaging: TOF PET
Florescence imaging
Other
Commercial:
CAEN (other companies interested but we will only work with one)
Other clients will show up when device available

20. Backup slides

21. L. Perktold / J. Christiansen
Time Measurements
Start - Stop Measurement
Measure relative time interval between two local events
Small local systems and low power applications
Time Tagging
Measure “absolute” time of an event (Relative to a time reference: clock)
For large scale systems with many channels all synchronized to the same reference
TWEPP 2013
L. Perktold / J. Christiansen

22. L. Perktold / J. Christiansen
TDC Architectures
1st stage
Counter extension
2nd stage
Multistage concept: Fine resolution Large dynamic range
TWEPP 2013
L. Perktold / J. Christiansen

23. Difficulties in ps range resolution
It is not worth making a fine binning TDC if resolution is lost in imperfections/noise
LSB/sqrt(12) ≠ rms
Device mismatch -> Careful simulation and optimization -> Major impact on design and performance
Noise (power supply) -> Short delays, fast edges -> Separate power domains -> Substrate isolation -> Crosstalk
Signal distribution critical -> RC delay of wires -> Balanced distribution of timing critical signals
Process-Voltage-Temperature variations -> Auto calibration to compensate for slow VT variations: Delay locked loop -> Global offset calibration still required
DNL, INL
Noise, Jitter
Single-shot
precision
Offset shifts

24. Fine-Time Interpolator
1.56 GHz
20 ps
delays
5 ps delays
DLL to control LSB size -> 32 fast delay elements in first stage - 20 ps -> Total delay of DLL 640 ps at 1.56 GHz
Resistive Interpolation to achieve sub - gate delay resolutions -> LSB size of 2nd stage controlled by DLL (Auto adjusts to DLL delay elements)
TWEPP 2013
L. Perktold / J. Christiansen

25. Reconstructed Transfer Function
after global calibration has been applied
channel 5
DNL
INL
TWEPP 2013
L. Perktold / J. Christiansen

26. Technology: URGENT Stay with IBM 130nm TSMC 130nm TSMC 65nm
Extend Lukas TDC macro to 64 channels + add counter registers
Reduce power consumption (will imply some loss in time resolution)
Add PLL
Make digital design based on HPTDC
Simplified and improved performance having individual data buffers per channel
SEU detection/immunity ? (export restrictions !)
Risk with IBM availability
TSMC 130nm
“Simple” technology mapping required
No design kit yet, Libraries ?
No performance improvement
No significant synergy with other projects
TSMC 65nm
Significant technology mapping required
Improved performance or architecture simplification and/or lower power
Simplify getting rid of second order resistive interpolation ?
Design kit and libraries available
Synergy with other projects: LPGBT, pixel chips
More expensive MPW and NRE
Make decision ASAP